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4.5.33. Secure Debug Control Register

The SDCR characteristics are:

Purpose

Controls debug and performance monitors functionality in Secure state.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RW-RWRW
Configurations

SDCR is mapped to AArch64 register MDCR_EL3.

Attributes

SDCR is a 32-bit register.

Figure 4.104 shows the SDCR bit assignments.

Figure 4.104. SDCR bit assignments

Figure 4.104. SDCR bit assignments

Table 4.209 shows the SDCR bit assignments

Table 4.209. SDCR bit assignments
BitsNameFunction
[31:22]-

Reserved, res0.

[21]EPMAD

External debugger access to Performance Monitors registers disabled. This disables access to these registers by an external debugger:

0

Access to Performance Monitors registers from external debugger is permitted. This is the reset value.

1

Access to Performance Monitors registers from external debugger is disabled, unless overridden by authentication interface.

[20]EDAD

External debugger access to breakpoint and watchpoint registers disabled. This disables access to these registers by an external debugger:

0

Access to breakpoint and watchpoint registers from external debugger is permitted. This is the reset value.

1

Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface.

[19:18]-

Reserved, res0.

[17]SPME

Secure performance monitors enable. This allows event counting in Secure state:

0

Event counting prohibited in Secure state, unless overridden by the authentication interface. This is the reset value.

1

Event counting allowed in Secure state.

[16]-

Reserved, res0.

[15:14]SPD

AArch32 secure privileged debug. Enables or disables debug exceptions in Secure state, other than Software breakpoint instructions. The possible values are:

0b00

Legacy mode. Debug exceptions from Secure EL1 are enabled by the authentication interface.

0b10

Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.

0b11

Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

The value 0b01 is reserved.

If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are also enabled.

Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.

SPD is ignored in Non-secure state. Debug exceptions from Software breakpoint instruction debug events are always enabled.

[13:0]-

Reserved, res0.


To access the SDCR:

MRC p15,0,<Rt>,c1,c3,1 ; Read SDCR into Rt
MCR p15,0,<Rt>,c1,c3,1 ; Write Rt to SDCR
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