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4.5.31. Secure Debug Enable Register

The SDER characteristics are:

Purpose

Controls invasive and non-invasive debug in the Secure EL0 state.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RW-RWRW
Configurations

SDER is architecturally mapped to AArch64 register SDER32_EL3. See Secure Debug Enable Register.

This register is accessible only in Secure state.

Attributes

SDER is a 32-bit register.

Figure 4.102 shows the SDER bit assignments.

Figure 4.102. SDER bit assignments

Figure 4.102. SDER bit assignments

Table 4.207 shows the SDER bit assignments.

Table 4.207. SDER bit assignments
BitsNameFunction
[31:2]-Reserved, res0.
[1]SUNIDEN

Secure User Non-invasive Debug Enable. The possible values are:

0

Non-invasive debug not permitted in Secure EL0 state. This is the Warm reset value.

1

Non-invasive debug permitted in Secure EL0 state.

[0]SUIDEN

Secure User Invasive Debug Enable. The possible values are:

0

Invasive debug not permitted in Secure EL0 state. This is the Warm reset value.

1

Invasive debug permitted in Secure EL0 state.


To access the SDER:

MRC p15,0,<Rt>,c1,c1,1 ; Read SDER into Rt
MCR p15,0,<Rt>,c1,c1,1 ; Write Rt to SDER
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