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4.5.42. Translation Table Base Control Register

The TTBCR characteristics are:

Purpose

Determines which of the Translation Table Base Registers defines the base address for a translation table walk required for the stage 1 translation of a memory access from any mode other than Hyp mode. Also controls the translation table format and, when using the Long-descriptor translation table format, holds cacheability and shareability information.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--RWRWRWRWRW

The processor does not use the implementation-defined bit, TTBCR[30], when using the Long-descriptor translation table format, so this bit is res0.

Configurations

TTBCR (NS) is architecturally mapped to AArch64 register TCR_EL1. See Translation Control Register, EL1.

If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.

Write access to the Secure instance of TTBCR is disabled if the CP15SDISABLE signal is asserted HIGH.

Attributes

TTBCR is a 32-bit register.

There are two formats for this register. TTBCR.EAE determines which format of the register is used. This section describes:

TTBCR format when using the Short-descriptor translation table format

Figure 4.115 shows the TTBCR bit assignments when TTBCR.EAE is 0.

Figure 4.115. TTBCR bit assignments, TTBCR.EAE is 0

Figure 4.115. TTBCR bit assignments, TTBCR.EAE
is 0

Table 4.220 shows the TTBCR bit assignments when TTBCR.EAE is 0.

Table 4.220. TTBCR bit assignments, TTBCR.EAE is 0
BitsNameFunction
[31]EAE

Extended Address Enable.

0

Use the 32-bit translation system, with the Short-descriptor translation table format.

[30:6]-

Reserved,res0.

[5]PD1

Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. The possible values are:

0

Perform translation table walks using TTBR1.

1

A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed.

[4]PD0

Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR0. The possible values are:

0

Perform translation table walks using TTBR0.

1

A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed.

[3]-

Reserved,res0.

[2:0]N

Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is bits[31:14-N]. The value of N also determines:

  • Whether TTBR0 or TTBR1 is used as the base address for translation table walks.

  • The size of the translation table pointed to by TTBR0.

N can take any value from 0 to 7, that is, from 0b000 to 0b111.

When N has its reset value of 0, the translation table base is compatible with Armv5 and Armv6.

Resets to 0.


TTBCR format when using the Long-descriptor translation table format

Figure 4.116 shows the TTBCR bit assignments when TTBCR.EAE is 1.

Figure 4.116. TTBCR bit assignments, TTBCR.EAE is 1

Figure 4.116. TTBCR bit assignments, TTBCR.EAE
is 1

Table 4.221 shows the TTBCR bit assignments when TTBCR.EAE is 1.signal

Table 4.221. TTBCR bit assignments, TTBCR.EAE is 1
BitsNameFunction
[31]EAE

Extended Address Enable:

1

Use the 40-bit translation system, with the Long-descriptor translation table format.

[30]-

Reserved,res0.

[29:28]SH1

Shareability attribute for memory associated with translation table walks using TTBR1:

0b00

Non-shareable.

0b10

Outer Shareable.

0b11

Inner Shareable.

Other values are reserved.

Resets to 0.

[27:26]ORGN1

Outer cacheability attribute for memory associated with translation table walks using TTBR1:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

Resets to 0.

[25:24]IRGN1

Inner cacheability attribute for memory associated with translation table walks using TTBR1:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

Resets to 0.

[23]EPD1

Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1:

0

Perform translation table walks using TTBR1.

1

A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed.

[22]A1

Selects whether TTBR0 or TTBR1 defines the ASID:

0

TTBR0.ASID defines the ASID.

1

TTBR1.ASID defines the ASID.

[21:19]-

Reserved,res0.

[18:16]T1SZ

The size offset of the memory region addressed by TTBR1. The region size is 232-T1SZ bytes.

Resets to 0.

[15:14]-

Reserved,res0.

[13:12]SH0

Shareability attribute for memory associated with translation table walks using TTBR0:

0b00

Non-shareable.

0b10

Outer Shareable.

0b11

Inner Shareable.

Other values are reserved.

Resets to 0.

[11:10]ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

Resets to 0.

[9:8]IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

Resets to 0.

[7]EPD0

Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0:

0

Perform translation table walks using TTBR0.

1

A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed.

[6:3]-

Reserved,res0.

[2:0]T0SZ

The size offset of the memory region addressed by TTBR0. The region size is 232-T0SZ bytes.

Resets to 0.


To access the TTBCR:

MRC p15,0,<Rt>,c2,c0,0 ; Read TTBR0 into Rt
MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0
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