The VBAR characteristics are:
Holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode when high exception vectors are not selected.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - RW RW RW RW RW
Software must program the Non-secure instance of the register with the required initial value as part of the processor boot sequence.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
The Non-secure VBAR is architecturally mapped to the AArch64 VBAR_EL1 register. See Vector Base Address Register, EL1.
The Secure VBAR is mapped to AArch64 register VBAR_EL3[31:0]. See Vector Base Address Register, EL3.
VBAR has write access to the Secure instance of the register disabled when the CP15SDISABLE signal is asserted HIGH.
VBAR is a 32-bit register.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
To access the VBAR:
MRC p15, 0, <Rt>, c12, c0, 0 ; Read VBAR into Rt MCR p15, 0, <Rt>, c12, c0, 0 ; Write Rt to VBAR