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4.4.9. c7 System operations

Table 4.138 shows the System operations when CRn is c7 and the processor is in AArch32 state. See the Arm® Architecture Reference Manual Armv8 for more information about these operations.

Table 4.138. c7 System operation summary
op1CRmop2NameDescription
0c10ICIALLUIS

Invalidate all instruction caches Inner Shareable to PoU[a]

 6BPIALLIS

Invalidate all entries from branch predictors Inner Shareable

 c50ICIALLU

Invalidate all Instruction Caches to PoU

 1ICIMVAU

Invalidate Instruction Caches by VA to PoU

 4CP15ISB

Instruction Synchronization Barrier operation, this operation is deprecated in Armv8-A

 6BPIALL

Invalidate all entries from branch predictors

 7BPIMVA

Invalidate VA from branch predictors

 c61DCIMVAC

Invalidate data cache line by VA to PoC[b]

 2DCISW

Invalidate data cache line by set/way

 c80ATS1CPR

Stage 1 current state PL1 read

 1ATS1CPW

Stage 1 current state PL1 write

 2ATS1CUR

Stage 1 current state unprivileged read

 3ATS1CUW

Stage 1 current state unprivileged write

 4ATS12NSOPR

Stages 1 and 2 Non-secure only PL1 read

 5ATS12NSOPW

Stages 1 and 2 Non-secure only PL1 write

 6ATS12NSOUR

Stages 1 and 2 Non-secure only unprivileged read

 7ATS12NSOUW

Stages 1 and 2 Non-secure only unprivileged write

 c101DCCMVAC

Clean data cache line by VA to PoC

 2DCCSW

Clean data cache line by set/way

 4CP15DSB

Data Synchronization Barrier operation, this operation is deprecated in Armv8-A

 5CP15DMB

Data Memory Barrier operation, this operation is deprecated in Armv8-A

 c111DCCMVAU

Clean data cache line by VA to PoU

 c141DCCIMVAC

Clean and invalidate data cache line by VA to PoC

 2DCCISW

Clean and invalidate data cache line by set/way

4c80ATS1HR

Stage 1 Hyp mode read

 1ATS1HW

Stage 1 Hyp mode write

[a] PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.

[b] PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.


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