The ID_ISAR5_EL1 characteristics are:
Provides information about the instruction sets that the processor implements.
The optional Advanced SIMD and Floating-point extension is not included in the base product of the processor. Arm requires licensees to have contractual rights to obtain the Advanced SIMD and Floating-point extension.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_ISAR5_EL1 is architecturally mapped to AArch32 register ID_ISAR5. See Instruction Set Attribute Register 5.
ID_ISAR5_EL1 is a 32-bit register.
Figure 4.16 shows the ID_ISAR5_EL1 bit assignments.
Table 4.48 shows the ID_ISAR5_EL1 bit assignments.
Indicates whether CRC32 instructions are implemented in AArch32 state:
Indicates whether SHA2 instructions are implemented in AArch32 state:
Indicates whether SHA1 instructions are implemented in AArch32 state:
Indicates whether AES instructions are implemented in AArch32 state:
Indicates whether the
To access the ID_ISAR5_EL1:
MRS <Xt>, ID_ISAR5_EL1 ; Read ID_ISAR5_EL1 into Xt
Register access is encoded as follows: