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4.3.8. AArch32 Memory Model Feature Register 0

The ID_MMFR0_EL1 characteristics are:

Purpose

Provides information about the memory model and memory management support in AArch32.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

ID_MMFR0_EL1 is architecturally mapped to AArch32 register ID_MMFR0. See Memory Model Feature Register 0.

Attributes

ID_MMFR0_EL1 is a 32-bit register.

Figure 4.7 shows the ID_MMFR0_EL1 bit assignments.

Figure 4.7. ID_MMFR0_EL1 bit assignments

Figure 4.7. ID_MMFR0_EL1 bit assignments

Table 4.30 shows the ID_MMFR0_EL1 bit assignments.

Table 4.30. ID_MMFR0_EL1 bit assignments
BitsNameFunction
[31:28]InnerShr

Indicates the innermost shareability domain implemented:

0x1

Implemented with hardware coherency support.

[27:24]FCSE

Indicates support for Fast Context Switch Extension (FCSE):

0x0

Not supported.

[23:20]AuxReg

Indicates support for Auxiliary registers:

0x2

Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register.

[19:16]TCM

Indicates support for TCMs and associated DMAs:

0x0

Not supported.

[15:12]ShareLvl

Indicates the number of shareability levels implemented:

0x1

Two levels of shareability implemented.

[11:8]OuterShr

Indicates the outermost shareability domain implemented:

0x1

Implemented with hardware coherency support.

[7:4]PMSA

Indicates support for a Protected Memory System Architecture (PMSA):

0x0

Not supported.

[3:0]VMSA

Indicates support for a Virtual Memory System Architecture (VMSA).

0x5

Support for:

  • VMSAv7, with support for remapping and the Access flag.

  • The PXN bit in the Short-descriptor translation table format descriptors.

  • The Long-descriptor translation table format.


To access the ID_MMFR0_EL1:

MRS <Xt>, ID_MMFR0_EL1 ; Read ID_MMFR0_EL1 into Xt

Register access is encoded as follows:

Table 4.31. ID_MMFR0_EL1 access encoding
op0op1CRnCRmop2
1100000000001100