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4.3.5. AArch32 Processor Feature Register 1

The ID_PFR1_EL1 characteristics are:

Purpose

Provides information about the programmers model and architecture extensions supported by the processor.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

-RORORORORO
Configurations

ID_PFR1_EL1 is architecturally mapped to AArch32 register ID_PFR1. See Processor Feature Register 1.

Attributes

ID_PFR1_EL1 is a 32-bit register.

Figure 4.5 shows the ID_PFR1_EL1 bit assignments.

Figure 4.5. ID_PFR1_EL1 bit assignments

Figure 4.5. ID_PFR1_EL1 bit assignments

Table 4.26 shows the ID_PFR1_EL1 bit assignments.

Table 4.26. ID_PFR1_EL1 bit assignments
BitsNameFunction
[31:28]GIC CPU

GIC CPU support:

0x0

GIC CPU interface is disabled, GICCDISABLE is HIGH.

0x1

GIC CPU interface is enabled.

[27:20]-Reserved, res0.
[19:16]GenTimer

Generic Timer support:

0x1

Generic Timer supported.

[15:12]Virtualization

Virtualization support:

0x1

Virtualization implemented.

[11:8]MProgMod

M profile programmers' model support:

0x0

Not supported.

[7:4]Security

Security support:

0x1

Security implemented. This includes support for Monitor mode and the SMC instruction.

[3:0]ProgMod

Indicates support for the standard programmers model for Armv4 and later.

Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:

0x1

Supported.


To access the ID_PFR1_EL1:

MRS <Xt>, ID_PFR1_EL1 ; Read ID_PFR1_EL1 into Xt

Register access is encoded as follows:

Table 4.27. REVIDR access encoding
op0op1CRnCRmop2
111100000000001001