The ID_PFR1_EL1 characteristics are:
Provides information about the programmers model and architecture extensions supported by the processor.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RO RO RO RO RO
ID_PFR1_EL1 is architecturally mapped to AArch32 register ID_PFR1. See Processor Feature Register 1.
ID_PFR1_EL1 is a 32-bit register.
Figure 4.5 shows the ID_PFR1_EL1 bit assignments.
Table 4.26 shows the ID_PFR1_EL1 bit assignments.
GIC CPU support:
Generic Timer support:
M profile programmers' model support:
Indicates support for the standard programmers model for Armv4 and later.
Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes:
To access the ID_PFR1_EL1:
MRS <Xt>, ID_PFR1_EL1 ; Read ID_PFR1_EL1 into Xt
Register access is encoded as follows: