The CSSELR_EL1 characteristics are:
Selects the current Cache Size ID Register, by specifying:
The required cache level.
The cache type, either instruction or data cache.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
CSSELR_EL1 is architecturally mapped to AArch32 register CSSELR(NS). See Cache Size Selection Register.
CSSELR_EL1 is a 32-bit register.
Figure 4.23 shows the CSSELR_EL1 bit assignments.
Table 4.62 shows the CSSELR_EL1 bit assignments.
To access the CSSELR_EL1:
MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1
Register access is encoded as follows: