The CPUACTLR_EL1 characteristics are:
Provides implementation defined configuration and control options for the processor. There is one 64-bit CPU Auxiliary Control Register for each core in the cluster.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- RW RW RW RW RW
The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.
Setting many of these bits can cause significantly lower performance on your code. Therefore, it is suggested that you do not modify this register unless directed by Arm.
Common to the Secure and Non-secure states.
Mapped to the AArch32 CPUACTLR register. CPU Auxiliary Control Register.
CPUACTLR_EL1 is a 64-bit register.
Figure 4.71 shows the CPUACTLR_EL1 bit assignments.
Table 4.124 shows the CPUACTLR_EL1 bit assignments.
Enable data cache clean as data cache clean/invalidate. The possible values are:
Disable floating-point dual issue. The possible values are:
Disable Dual Issue. The possible values are:
Write streaming no-allocate threshold. The possible values are:
Write streaming no-L1-allocate threshold. The possible values are:
Disable transient and no-read-allocate hints for loads. The possible values are:
Disable ReadUnique request for prefetch streams initiated by STB accesses:
Disable prefetch streams initiated from STB accesses:
IFU fetch throttle disabled. The possible values are:
Number of independent data prefetch streams. The possible values are:
Enable device split throttle. The possible values are:
Configure the sequence length that triggers data prefetch streams. The possible values are:
In both configurations, Three linefills with a fixed stride pattern are required to trigger prefetch, if the stride spans more than one cache line.
L1 Data prefetch control. The value of this field determines the maximum number of outstanding data prefetches allowed in the L1 memory system, excluding those generated by software load or PLD instructions. The possible values are:
Disable optimized Data Memory Barrier behavior. The possible values are:
L1 D-cache data RAM error injection enable. The possible values are:
To access the CPUACTLR_EL1:
MRS <Xt>, S3_1_C15_C2_0 ; Read EL1 CPU Auxiliary Control Register MSR S3_1_C15_C2_0, <Xt> ; Write EL1 CPU Auxiliary Control Register