The ESR_EL1 characteristics are:
- Purpose
Holds syndrome information for an exception taken to EL1.
- Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2 EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW - Configurations
ESR_EL1 is architecturally mapped to AArch32 register DFSR (NS). See Data Fault Status Register.
- Attributes
ESR_EL1 is a 32-bit register.
Figure 4.50 shows the ESR_EL1 bit assignments.
Table 4.94 shows the ESR_EL1 bit assignments.
| Bits | Name | Function |
|---|---|---|
| [31:26] | EC | Exception Class. Indicates the reason for the exception that this register holds information about. |
| [25] | IL | Instruction Length for synchronous exceptions. The possible values are:
This field
is 1 for the SError interrupt, instruction aborts, misaligned PC, Stack
pointer misalignment, data aborts for which the ISV bit is 0, exceptions
caused by an illegal instruction set state, and exceptions using
the |
| [24] | ISS Valid | Syndrome valid. The possible values are:
|
| [23:0] | ISS | Syndrome information. |
When the EC field is 0x2F, indicating an
SError interrupt has occurred, the ISS field contents are IMPLEMENTATION
DEFINED. Table 4.95 shows
the definition of the ISS field contents for the Cortex-A53 processor.
| ISS[23:22] | ISS[1:0] | Description |
|---|---|---|
0b00 | 0b00 | DECERR on external access |
0b00 | 0b01 | Double-bit error detected on dirty line in L2 cache |
0b00 | 0b10 | SLVERR on external access |
0b01 | 0b00 | nSEI, or nVSEI in a guest OS, asserted |
0b01 | 0b01 | nREI asserted |
To access the ESR_EL1:
MRS <Xt>, ESR_EL1 ; Read EL1 Exception Syndrome Register MSR ESR_EL1, <Xt> ; Write EL1 Exception Syndrome Register