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4.3.63. Hypervisor IPA Fault Address Register, EL2

The HPFAR_EL2 characteristics are:

Purpose

Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RWRWRW
Configurations

HPFAR_EL2[31:0] is mapped to AArch32 register HPFAR. See Hyp IPA Fault Address Register.

Attributes

HPFAR_EL2 is a 64-bit register.

Figure 4.57 shows the HPFAR_EL2 bit assignments.

Figure 4.57. HPFAR_EL2 bit assignments

Figure 4.57. HPFAR_EL2 bit assignments

Table 4.106 Table 4.104 shows the HPFAR_EL2 bit assignments.

Table 4.106.  HPFAR_EL2 bit assignments
BitsNameFunction
[63:40]-

Reserved, res0.

[39:4]FIPA[47:12]

Bits [47:12] of the faulting intermediate physical address. The equivalent upper bits in this field are res0.

[3:0]-

Reserved, res0.


To access the HPFAR_EL:

MRS <Xt>, HPFAR_EL2 ; Read EL2 Fault Address Register
MSR HPFAR_EL2, <Xt> ; Write EL2 Fault Address Register