The MAIR_EL2 characteristics are:
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL2.
- Usage constraints
This register is accessible as follows:
(SCR.NS = 1)
(SCR.NS = 0)
- - - RW RW RW
MAIR_EL2 is permitted to be cached in a TLB.
MAIR_EL2[31:0] is architecturally mapped to AArch32 register HMAIR0.
MAIR_EL2[63:32] is architecturally mapped to AArch32 register HMAIR1.
MAIR_EL2 is a 64-bit register.
The MAIR_EL2 bit assignments follow the same pattern as described in Figure 4.64.
To access the MAIR_EL2:
MRS <Xt>, MAIR_EL2 ; Read EL2 Memory Attribute Indirection Register MSR MAIR_EL2, <Xt> ; Write EL2 Memory Attribute Indirection Register