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4.3.73. Vector Base Address Register, EL2

The VBAR_EL2 characteristics are:

Purpose

Holds the exception base address for any exception that is taken to EL2.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RWRWRW
Configurations

The VBAR_EL2[31:0] is architecturally mapped to the AArch32 HVBAR register. See Hyp Vector Base Address Register.

Attributes

VBAR_EL2 is a 64-bit register.

Figure 4.66 shows the VBAR_EL2 bit assignments.

Figure 4.66. VBAR_EL2 bit assignments

Figure 4.66. VBAR_EL2 bit assignments

Table 4.117 shows the VBAR_EL2 bit assignments.

Table 4.117.  VBAR_EL2 bit assignments
BitsNameFunction
[63:11]Vector base address

Base address of the exception vectors for exceptions taken in this exception level.

[10:0]-

Reserved, res0.


To access the VBAR_EL2:

MRS <Xt>, VBAR_EL2 ; Read VBAR_EL2 into Xt
MSR VBAR_EL2, <Xt> ; Write Xt to VBAR_EL2

Register access is encoded as follows:

Table 4.118. VBAR_EL2 access encoding
op0op1CRnCRmop2
1110011000000000