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4.1.1. AArch32 registers affected by CP15SDISABLE

In AArch32 state, the CP15SDISABLE input disables write access to certain system registers.

The Cortex-A53 processor does not have any implementation defined registers that are affected by CP15SDISABLE.

For a list of registers affected by CP15SDISABLE, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.