This appendix describes specific Cortex-A53 processor unpredictable behaviors of particular interest. For AArch32 execution, the Armv8-A architecture specifies a much narrower range of legal behaviors for the cases that in Armv7 were described as unpredictable. See Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile. This gives considerable background on this topic and documents these unpredictable behaviors in these sections:
A range of legal behaviors for each unpredictable case.
A single preferred behavior for each unpredictable case from that range of legal behaviors.
Where possible and practical, all Arm implementations adhere to these single preferred behaviors. In some limited instances an Arm implementation might not adhere to these single preferred behaviors, and instead behaves as described by one of the alternate legal behaviors.The purpose of this appendix is to document all such instances where the Cortex-A53 processor implementation diverges from the preferred behavior described in Armv8 AArch32 unpredictable behaviors, and to describe exactly which of the remaining alternative behaviors is implemented.
This appendix contains the following sections: