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11.11.5. Component Identification Registers

There are four read-only Component Identification Registers, Component ID0 through Component ID3. Table 11.38 shows these registers.

Table 11.38. Summary of the ROM table component Identification registers
RegisterValueOffset
ROMCIDR00x0D0xFF0
ROMCIDR10x100xFF4
ROMCIDR20x050xFF8
ROMCIDR30xB10xFFC

The Component Identification Registers identify Debug as an Arm Debug Interface v5 component. The ROM table Component ID registers are:

Component Identification Register 0

The ROMCIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLKOSLKEDADSLKDefault
-----RO

Table 11.1 describes the condition codes.

Configurations

The ROMCIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 11.28.

Figure 11.27 shows the ROMCIDR0 bit assignments.

Figure 11.27. ROMCIDR0 bit assignments

Figure 11.27. ROMCIDR0 bit assignments

Table 11.39 shows the ROMCIDR0 bit assignments.

Table 11.39. ROMCIDR0 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]Size
0x0D

Preamble byte 0.


The ROMCIDR0 can be accessed through the external debug interface, offset 0xFF0.

Component Identification Register 1

The ROMCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLKOSLKEDADSLKDefault
-----RO

Table 11.1 describes the condition codes.

Configurations

The ROMCIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 11.28.

Figure 11.28 shows the ROMCIDR1 bit assignments.

Figure 11.28. ROMCIDR1 bit assignments

Figure 11.28. ROMCIDR1 bit assignments

Table 11.40 shows the ROMCIDR1 bit assignments.

Table 11.40. ROMCIDR1 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]CLASS
0x1

Component Class. For a ROM table.

[3:0]PRMBL_1
0x0

Preamble.


The ROMCIDR1 can be accessed through the external debug interface, offset 0xFF4.

Component Identification Register 2

The ROMCIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLKOSLKEDADSLKDefault
-----RO

Table 11.1 describes the condition codes.

Configurations

The ROMCIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 11.28.

Figure 11.29 shows the ROMCIDR2 bit assignments.

Figure 11.29. ROMCIDR2 bit assignments

Figure 11.29. ROMCIDR2 bit assignments

Table 11.41 shows the ROMCIDR2 bit assignments.

Table 11.41. ROMCIDR2 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_2
0x05

Preamble byte 2.


The ROMCIDR2 can be accessed through the external debug interface, offset 0xFF8.

Component Identification Register 3

The ROMCIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

This register is accessible as follows:

Off DLKOSLKEDADSLKDefault
-----RO

Table 11.1 describes the condition codes.

Configurations

The ROMCIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 11.28.

Figure 11.30 shows the ROMCIDR3 bit assignments.

Figure 11.30. ROMCIDR3 bit assignments

Figure 11.30. ROMCIDR3 bit assignments

Table 11.42 shows the ROMCIDR3 bit assignments.

Table 11.42. ROMCIDR3 bit assignments
BitsNameFunction
[31:8]-

Reserved, res0.

[7:0]PRMBL_3
0xB1

Preamble byte 3.


The ROMCIDR3 can be accessed through the external debug interface, offset 0xFFC.

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