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13.2. ETM trace unit generation options and resources

Table 13.1 shows the trace generation options implemented in the Cortex-A53 ETM trace unit.

Table 13.1. ETM trace unit generation options implemented
DescriptionConfiguration
Instruction address size in bytes8
Data address size in bytes 0
Data value size in bytes0
Virtual Machine ID size in bytes 1
Context ID size in bytes4
Support for conditional instruction tracingNot implemented
Support for tracing of dataNot implemented
Support for tracing of load and store instructions as P0 elementsNot implemented
Support for cycle counting in the instruction traceImplemented
Support for branch broadcast tracingImplemented
Exception Levels implemented in Non-secure stateEL2, EL1, EL0
Exception Levels implemented in Secure stateEL3, EL1, EL0
Number of events supported in the trace4
Return stack supportImplemented
Tracing of SError exception supportImplemented
Instruction trace cycle counting minimum threshold 1
Size of Trace ID7 bits
Synchronization period supportRead-write
Global timestamp size64 bits
Number of cores available for tracing1
ATB trigger support Implemented
Low power behavior overrideImplemented
Stall control supportImplemented
Support for no overflows in the traceNot implemented

Table 13.2 shows the resources implemented in the Cortex-A53 ETM trace unit.

Table 13.2. ETM trace unit resources implemented
DescriptionConfiguration
Number of resource selection pairs implemented8
Number of external input selectors implemented4
Number of external inputs implemented 30, 4 CTI + 26 PMU
Number of counters implemented 2
Reduced function counter implemented Not implemented
Number of sequencer states implemented4
Number of Virtual Machine ID comparators implemented 1
Number of Context ID comparators implemented1
Number of address comparator pairs implemented4
Number of single-shot comparator controls1
Number of processor comparator inputs implemented 0
Data address comparisons implementedNot implemented
Number of data value comparators implemented 0

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