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9.2.3. CPU interface register descriptions

This section describes only registers whose implementation is specific to the Cortex-A53 processor. All other registers are described in the Arm® Generic Interrupt Controller Architecture Specification Table 9.2 provides cross-references to individual registers.

Active Priority Register

The GICC_APR0 characteristics are:

Purpose

Provides support for preserving and restoring state in power management applications.

Usage constraints

This register is banked to provide Secure and Non-secure copies. This ensures that Non-secure accesses do not interfere with Secure operation.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

The Cortex-A53 processor implements the GICC_APR0 according to the recommendations described in the Arm® Generic Interrupt Controller Architecture Specification.

Table 9.5 shows the Cortex-A53 MPCore GICC_APR0 implementation.

Table 9.5. Active Priority Register implementation
Number of group priority bitsPreemption levelsMinimum legal value of Secure GICC_BPRMinimum legal value of Non-secure GICC_BPRActive Priority Registers implementedView of Active Priority Registers for Non-secure accesses
53223GICC_APR0 [31:0]

GICC_NSAPR0 [31:16] appears as GICC_APR0 [15:0]


CPU Interface Identification Register

The GICC_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the CPU interface.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.2.

Figure 9.1 shows the GICC_IIDR bit assignments.

Figure 9.1. GICC_IIDR bit assignments

Figure 9.1. GICC_IIDR bit assignments

Table 9.6 shows the GICC_IIDR bit assignments.

Table 9.6. GICC_IIDR bit assignments
BitNameFunction
[31:20]ProductID

Identifies the product:

0x003

Cortex-A53 processor.

[19:16] Architecture version

Identifies the architecture version of the GICCPU Interface:

0x4

GICv4.

[15:12]Revision

Identifies the revision number for the CPU interface:

0x4

r0p4.

[11:0] Implementer

Contains the JEP106 code of the company that implements the CPU interface. For an Arm implementation, these values are:

Bits[11:8] = 0x4

The JEP106 continuation code of the implementer.

Bit[7]

Always 0.

Bits[6:0] = 0x3B

The JEP106 identity code of the implementer.


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