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9.2.2. CPU interface register summary

Each CPU interface block provides the interface for a Cortex-A53 processor that interfaces with a GIC distributor within the system. Each CPU interface provides a programming interface for:

  • Enabling the signaling of interrupt requests by the CPU interface.

  • Acknowledging an interrupt.

  • Indicating completion of the processing of an interrupt.

  • Setting an interrupt priority mask for the processor.

  • Defining the preemption policy for the processor.

  • Determining the highest priority pending interrupt for the processor.

  • Generating SGIs.

For more information on the CPU interface, see the Arm Generic Interrupt Controller Architecture Specification.

Table 9.2 lists the registers for the CPU interface.

Note

Accesses to the GICC memory space that do not target documented registers will generate an AXI/CHI slave error abort.

All the registers in Table 9.2 are word-accessible. Registers not described in this table are res0. See the Arm® Generic Interrupt Controller Architecture Specification for more information.

Table 9.2. CPU interface register summary
OffsetNameTypeResetDescription
0x0000GICC_CTLRRW0x00000000CPU Interface Control Register
0x0004GICC_PMRRW0x00000000Interrupt Priority Mask Register
0x0008GICC_BPRRW

0x00000002 (S)[a]

0x00000003 (NS)[b]

Binary Point Register
0x000CGICC_IARRO-Interrupt Acknowledge Register
0x0010GICC_EOIRWO-End Of Interrupt Register
0x0014GICC_RPRRO0x000000FFRunning Priority Register
0x0018GICC_HPPIRRO0x000003FFHighest Priority Pending Interrupt Register
0x001CGICC_ABPRRW0x00000003Aliased Binary Point Register
0x0020GICC_AIARRO-

Aliased Interrupt Acknowledge Register

0x0024GICC_AEOIRWO-

Aliased End of Interrupt Register

0x0028GICC_AHPPIRRO0x000003FF

Aliased Highest Priority Pending Interrupt Register

0x00D0GICC_APR0RW0x00000000Active Priority Register
0x00E0GICC_NSAPR0RW0x00000000Non-secure Active Priority Register
0x00FCGICC_IIDRRO0x0034443BCPU Interface Identification Register
0x1000GICC_DIRWO-Deactivate Interrupt Register

[a] S = Secure.

[b] NS = Non-secure.


The following table shows the system accesses for the CPU interface in AArch32.

Table 9.3. AArch32 GIC CPU interface system accesses
NameCRnop1CRmop2TypeDescription
ICC_PMRc40c60RWPriority Mask Register
ICC_IAR0c120 0R0Group0 Interrupt Acknowledge Register
ICC_EOIR0  c81WOGroup0 End of Interrupt Register
ICC_HPPIR0  2R0Group0 Highest Priority Pending Interrupt Register
ICC_BPR0  3RWGroup0 Binary Pointer Register
ICC_AP0R0  4RW Active Priority Group0 Register
ICC_AP1R0  c90RW Active Priority Group1 Register
ICC_DIR  c111WODeactivate Register
ICC_RPR   3RORunning Priority Register
ICC_IAR1  c120ROGroup1 Interrupt Acknowledge Register
ICC_EOIR1  1WOGroup1 End of Interrupt Register
ICC_HPPIR1  2ROGroup1 Highest Priority Pending Interrupt Register
ICC_BPR1  3RW B[a]Group1 Binary Pointer Register
ICC_CTLR  4RW BControl Register
ICC_SRE  5RW BSystem Register Enable
ICC_IGRPEN0  6RW BGroup0 Interrupt Group Enable
ICC_IGRPEN1  7RWGroup1 Interrupt Group Enable
ICC_SGI1R[b]  -RW BGroup1 Software Generated Interrupt Register
ICC_ASGI1R 0c12-WOAliased Group1 Software Generated Interrupt Register
ICC_SGI0R 2c12-WOGroup0 Software Generated Interrupt Register
ICC_MCTLR 6c124RWMonitor Control Register
ICC_MSRE  5RWMonitor System Register Enable
ICC_MGRPEN1  7RWMonitor Group1 Interrupt Group Enable

[a] When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.

[b] Use MCRR instructions to access this register in AArch32 state.


The following table shows the system accesses for the GIC CPU interface in AArch64.

Table 9.4. AArch64 GIC CPU interface system accesses
NameTypeDescription
ICC_PMR_EL1RWPriority Mask Register
ICC_IAR0_EL1ROGroup0 Interrupt Acknowledge Register
ICC_EOIR0_EL1WOGroup0 End of Interrupt Register
ICC_HPPIR0_EL1ROGroup0 Highest Priority Pending Interrupt Register
ICC_BPR0_EL1RWGroup0 Binary Pointer Register
ICC_AP0R0_EL1RW Active Priority Group0 Register
ICC_AP1R0_EL1RW Active Priority Group1 Register
ICC_DIR_EL1WODeactivate Register
ICC_RPR_EL1RORunning Priority Register
ICC_SGI1R_EL1WOGroup1 Software Generated Interrupt Register
ICC_ASGI1R_EL1WOAliased Group1 Software Generated Interrupt Register
ICC_SGI0R_EL1WOGroup0 Software Generated Interrupt Register
ICC_IAR1_EL1ROGroup1 Interrupt Acknowledge Register
ICC_EOIR1_EL1WOGroup1 End of Interrupt Register
ICC_HPPIR1_EL1ROGroup1 Highest Priority Pending Interrupt Register
ICC_BPR1_EL1RW B[a]Group1 Binary Pointer Register
ICC_CTLR_EL1RW BControl Register
ICC_SRE_EL1RW BSystem Register Enable
ICC_IGRPEN0_EL1RWGroup0 Interrupt Group Enable Register
ICC_IGRPEN1_EL1RW BGroup1 Interrupt Group Enable
ICC_CTLRRWEL3 Control Register
ICC_SRE_EL3RWEL3 System Register Enable
ICC_GRPEN1_EL3RWEL3 Group1 Interrupt Group Enable

[a] When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.


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