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9.2.5. Virtual interface control register descriptions

This section describes only registers whose implementation is specific to the Cortex-A53 processor. All other registers are described in the Arm® Generic Interrupt Controller Architecture Specification. Table 9.7 provides cross-references to individual registers.

VGIC Type Register

The GICH_VTR characteristics are:

Purpose

Holds information on number of priority bits, number of preemption bits, and number of List Registers implemented.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.7.

Figure 9.2 shows the GICH_VTR bit assignments.

Figure 9.2. GICH_VTR bit assignments

Figure 9.2. GICH_VTR bit assignments

Table 9.10 shows the GICH_VTR bit assignments.

Table 9.10. GICH_VTR bit assignments
Bit Name Description
[31:29] PRIbits

Indicates the number of priority bits implemented, minus one:

0x4

Five bits of priority and 32 priority levels.

[28:26]PREbits

Indicates the number of preemption bits implemented, minus one:

0x4

Five bits of preemption and 32 preemption levels.

[25:6]-Reserved, res0.
[5:0]ListRegs

Indicates the number of implemented List Registers, minus one:

0x3

Four List Registers.


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