You copied the Doc URL to your clipboard.

9.2.4. Virtual interface control register summary

The virtual interface control registers are management registers. Configuration software on the Cortex-A53 processor must ensure they are accessible only by a hypervisor, or similar software.

Table 9.7 describes the registers for the virtual interface control registers.

All the registers in Table 9.7 are word-accessible. Registers not described in this table are res0. See the Arm® Generic Interrupt Controller Architecture Specification for more information.

Table 9.7. Virtual interface control register summary
OffsetNameTypeResetDescription
0x000GICH_HCRRW0x00000000Hypervisor Control Register
0x004GICH_VTRRO0x90000003VGIC Type Register
0x008GICH_VMCRRW0x004C0000

Virtual Machine Control Register

0x010GICH_MISRRO0x00000000

Maintenance Interrupt Status Register

0x020GICH_EISR0RO0x00000000

End of Interrupt Status Registers

0x030GICH_ELRSR0RO0x0000000F

Empty List Register Status Registers

0x0F0GICH_APR0RW0x00000000Active Priorities Register
0x100GICH_LR0RW0x00000000List Register 0
0x104GICH_LR1RW0x00000000List Register 1
0x108GICH_LR2RW0x00000000List Register 2
0x10CGICH_LR3RW0x00000000List Register 3

The following table shows the register map for the AArch32 virtual interface System registers.

Table 9.8. AArch32 virtual interface System register summary
NameCRnop1CRmop2TypeDescription
ICH_APR0c124c80RWHypervisor Active Priority Register 0
ICH_APR1  c90RWHypervisor Active Priority Register 1
ICH_VSEIR  4RWVirtual System Error Interrupt Register
ICH_SRE  5RWHypervisor System Register
ICH_HCR 4c110RWHypervisor Control Register
ICH_VTR  1ROVGIC Type Register
ICH_MISR  2ROMaintenance Interrupt Status Register
ICH_EISR  3ROEnd of Interrupt Status Register
ICH_ELRSR  5ROEmpty List Register Status Register
ICH_VMCR  7RWVirtual Machine Control Register
ICH_LR0  c120RWList Register 0 to 3
ICH_LR1   1RW
ICH_LR2   2RW
ICH_LR3   3RW
ICH_LRC0  c140RWList Register Extension 0 to 3
ICH_LRC1   1RW
ICH_LRC2   2RW
ICH_LRC3   3RW

The following table shows the register map for the AArch64 virtual interface System registers.

Table 9.9. AArch64 virtual interface System register summary
NameTypeDescription
ICH_APR0_EL2RWHypervisor Active Priority Register
ICH_VSEIR_EL2RWVirtual System Error Interrupt Register
ICH_HCR_EL2RWHypervisor Control Register
ICH_VTR_EL2RWVGIC Type Register
ICC_SRE_EL2RWHypervisor System Register Enable
ICH_MISR_EL2RWMaintenance Interrupt Status Register
ICH_EISR_EL2RWEnd of Interrupt Status Register
ICH_ELRSR_EL2RWEmpty List Register Status Register
ICH_VMCR_EL2RWVirtual Machine Control Register
ICH_LR0_EL2RWList Register 0
ICH_LR1_EL2RWList Register 1
ICH_LR2_EL2RWList Register 2
ICH_LR3_EL2RWList Register 3

Was this page helpful? Yes No