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6.7. Direct access to internal memory

The Cortex-A53 processor provides a mechanism to read the internal memory used by the Cache and TLB structures through implementation-defined system registers. This functionality can be useful when investigating issues where the coherency between the data in the cache and data in system memory is broken.

When the processor is using AArch64, the appropriate memory block and location are selected using a number of write-only registers and the data is read from read-only registers as shown in Table 6.5. These operations are available only in EL3. In all other modes, executing these instruction results in an Undefined Instruction exception.

Table 6.4. AArch64 registers used to access internal memory
FunctionAccessOperationRd Data
Data Register 0Read-onlyMRS <Xd>, S3_3_c15_c0_0Data
Data Register 1Read-onlyMRS <Xd>, S3_3_c15_c0_1Data
Data Register 2Read-onlyMRS <Xd>, S3_3_c15_c0_2Data
Data Register 3Read-onlyMRS <Xd>, S3_3_c15_c0_3Data
Data Cache Tag Read Operation RegisterWrite-onlyMSR S3_3_c15_c2_0, <Xd>Set/Way
Instruction Cache Tag Read Operation RegisterWrite-onlyMSR S3_3_c15_c2_1, <Xd>Set/Way
Data Cache Data Read Operation RegisterWrite-onlyMSR S3_3_c15_c4_0, <Xd>Set/Way/Offset
Instruction Cache Data Read Operation RegisterWrite-onlyMSR S3_3_c15_c4_1, <Xd>Set/Way/Offset
TLB Data Read Operation RegisterWrite-onlyMSR S3_3_c15_c4_2, <Xd>Index/Way

When the processor is using AArch32, the appropriate memory block and location are selected using a number of write-only CP15 registers and the data is read from read-only CP15 registers as shown in Table 6.5. These operations are available only in EL3. In all other modes, executing the CP15 instruction results in an Undefined Instruction exception.

Table 6.5. AArch32 CP15 registers used to access internal memory
FunctionAccessCP15 operationRd Data
Data Register 0Read-onlyMRC p15, 3, <Rd>, c15, c0, 0Data
Data Register 1Read-onlyMRC p15, 3, <Rd>, c15, c0, 1Data
Data Register 2Read-onlyMRC p15, 3, <Rd>, c15, c0, 2Data
Data Register 3Read-onlyMRC p15, 3, <Rd>, c15, c0, 3Data
Data Cache Tag Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c2, 0Set/Way
Instruction Cache Tag Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c2, 1Set/Way
Data Cache Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 0Set/Way/Offset
Instruction Cache Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 1Set/Way/Offset
TLB Data Read Operation RegisterWrite-onlyMCR p15, 3, <Rd>, c15, c4, 2Index/Way

The following sections describe the encodings for the operations and the format for the data read from the memory:

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