You copied the Doc URL to your clipboard.

7.6.1. External aborts handling

The memory system handles external aborts using the synchronous abort mechanism, asynchronous abort mechanism, or nEXTERRIRQ pin as follows:

Synchronous abort mechanisms

External aborts on the following accesses use the synchronous abort mechanism:

  • All load accesses.

  • All Store Exclusive accesses (STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP).

Asyncronous abort mechanisms

External aborts on the following accesses use the asynchronous abort mechanism:

  • Stores to Device memory (except Store Exclusive accesses).

  • Stores to Normal memory that is Inner Non-cacheable, Inner Write-Through, Outer Non-cacheable, or Outer Write-Through (except Store Exclusive accesses).

  • L1 data cache and L2 cache linefills that receive data from the interconnect in the dirty state.

nEXTERRIRQ pin

External aborts on the following accesses cause the nEXTERRIRQ pin to be asserted because the aborts might not relate directly back to a specific core in the cluster.

  • All store accesses to Normal memory that is both Inner Write-Back and Outer Write-Back.

  • Evictions from the L1 data cache or L2 cache.

  • DVM Complete transactions.

Note

When nEXTERRIRQ is asserted it remains asserted until the error is cleared by a write of 0 to the AXI or CHI asynchronous error bit of the L2ECTLR register.

Was this page helpful? Yes No