You copied the Doc URL to your clipboard.

12.6.1. Performance Monitors Control Register

The PMCR characteristics are:

Purpose

Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

ConfigConfigRWRWRWRWRW

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.

Configurations

The PMCR is architecturally mapped to:

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

PMCR is a 32-bit register.

Figure 12.5 shows the PMCR bit assignments.

Figure 12.5. PMCR bit assignments

Figure 12.5. PMCR bit assignments

Table 12.10 shows the PMCR bit assignments.

Table 12.10. PMCR bit assignments
BitsNameFunction
[31:24]IMP

Implementer code:

0x41

Arm.

This is a read-only field.

[23:16]IDCODE

Identification code:

0x03

Cortex-A53.

This is a read-only field.

[15:11]N

Number of event counters.

0b00110

Six counters.

[10:7]-

Reserved, res0.

[6]LC

Long cycle count enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded in PMOVSR[31]. The possible values are:

0

Overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0.

1

Overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0.

[5]DP

Disable cycle counter, PMCCNTR_EL0 when event counting is prohibited:

0

Cycle counter operates regardless of the non-invasive debug authentication settings. This is the reset value.

1

Cycle counter is disabled if non-invasive debug is not permitted and enabled.

This bit is read/write.

[4]X

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:

0

Export of events is disabled. This is the reset value.

1

Export of events is enabled.

This bit is read/write and does not affect the generation of Performance Monitors interrupts on the nPMUIRQ pin.

[3]D

Clock divider:

0

When enabled, PMCCNTR_EL0 counts every clock cycle. This is the reset value.

1

When enabled, PMCCNTR_EL0 counts every 64 clock cycles.

This bit is read/write.

[2]C

Clock counter reset. This bit is WO. The effects of writing to this bit are:

0

No action. This is the reset value.

1

Reset PMCCNTR_EL0 to 0.

This bit is always RAZ.

Note

Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

[1]P

Event counter reset. This bit is WO. The effects of writing to this bit are:

0

No action. This is the reset value.

1

Reset all event counters, not including PMCCNTR_EL0, to zero.

This bit is always RAZ.

In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that MDCR_EL2.HPMN reserves for EL2 use.

In EL2 and EL3, a write of 1 to this bit resets all the event counters.

Resetting the event counters does not clear any overflow bits to 0.

[0]E

Enable. The possible values of this bit are:

0

All counters, including PMCCNTR_EL0, are disabled. This is the reset value.

1

All counters are enabled.

This bit is RW.

In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that MDCR_EL2.HPMN reserves for EL2 use.

On Warm reset, the field resets to 0.


To access the PMCR:

MRC p15, 0, <Rt>, c9, c12, 0 ; Read PMCR into Rt
MCR p15, 0, <Rt>, c9, c12, 0 ; Write Rt to PMCR

The PMCR can be accessed through the external debug interface, offset 0xE04.

Was this page helpful? Yes No