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12.4.2. Performance Monitors Common Event Identification Register 0

The PMCEID0_EL0 characteristics are:

Purpose

Defines which common architectural and common microarchitectural feature events are implemented.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

ConfigRORORORORO

This register is accessible at EL0 when PMUSERENR_EL0.EN is set to 1.

Configurations

The PMCEID0_EL0 is architecturally mapped to:

Attributes

PMCEID0_EL0 is a 32-bit register.

Figure 12.3 shows the PMCEID0_EL0 bit assignments.

Figure 12.3. PMCEID0_EL0 bit assignments

Figure 12.3. PMCEID0_EL0 bit assignments

Table 12.6 shows the PMCEID0_EL0 bit assignments

Table 12.5. PMCEID0_EL0 bit assignments
BitsNameFunction
[31:0]CE[31:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in Table 12.6, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.


Table 12.6. PMU common events
BitEvent numberEvent mnemonicDescription
[31]0x1FL1D_CACHE_ALLOCATE

L1 Data cache allocate:

0

This event is not implemented.

[30]0x1ECHAIN

Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count:

1

This event is implemented.

[29]0x1DBUS_CYCLES

Bus cycle:

1

This event is implemented.

[28]0x1CTTBR_WRITE_RETIRED

TTBR write, architecturally executed, condition check pass - write to translation table base:

0

This event is not implemented.

[27]0x1BINST_SPEC

Instruction speculatively executed:

0

This event is not implemented.

[26]0x1AMEMORY_ERROR

Local memory error:

1

This event is implemented.

[25]0x19BUS_ACCESS

Bus access:

1

This event is implemented.

[24]0x18L2D_CACHE_WB

L2 Data cache Write-Back:

0

This event is not implemented if the Cortex-A53 processor has been configured without an L2 cache.

1

This event is implemented if the Cortex-A53 processor has been configured with an L2 cache.

[23]0x17L2D_CACHE_REFILL

L2 Data cache refill:

0

This event is not implemented if the Cortex-A53 processor has been configured without an L2 cache.

1

This event is implemented if the Cortex-A53 processor has been configured with an L2 cache.

[22]0x16L2D_CACHE

L2 Data cache access:

0

This event is not implemented if the Cortex-A53 processor has been configured without an L2 cache.

1

This event is implemented if the Cortex-A53 processor has been configured with an L2 cache.

[21]0x15L1D_CACHE_WB

L1 Data cache Write-Back:

1

This event is implemented.

[20]0x14L1I_CACHE

L1 Instruction cache access:

1

This event is implemented.

[19]0x13MEM_ACCESS

Data memory access:

1

This event is implemented.

[18]0x12BR_PRED

Predictable branch speculatively executed:

1

This event is implemented.

[17]0x11CPU_CYCLES

Cycle:

1

This event is implemented.

[16]0x10BR_MIS_PRED

Mispredicted or not predicted branch speculatively executed:

1

This event is implemented.

[15]0x0FUNALIGNED_LDST_RETIRED

Instruction architecturally executed, condition check pass - unaligned load or store:

1

This event is implemented.

[14]0x0EBR_RETURN_RETIRED

Instruction architecturally executed, condition check pass - procedure return:

0

This event is not implemented.

[13]0x0DBR_IMMED_RETIRED

Instruction architecturally executed - immediate branch:

1

This event is implemented.

[12]0x0CPC_WRITE_RETIRED

Instruction architecturally executed, condition check pass - software change of the PC:

1

This event is implemented.

[11]0x0BCID_WRITE_RETIRED

Instruction architecturally executed, condition check pass - write to CONTEXTIDR:

1

This event is implemented.

[10]0x0AEXC_RETURN

Instruction architecturally executed, condition check pass - exception return:

1

This event is implemented.

[9]0x09EXC_TAKEN

Exception taken:

1

This event is implemented.

[8]0x08INST_RETIRED

Instruction architecturally executed:

1

This event is implemented.

[7]0x07ST_RETIRED

Instruction architecturally executed, condition check pass - store:

1

This event is implemented.

[6]0x06LD_RETIRED

Instruction architecturally executed, condition check pass - load:

1

This event is implemented.

[5]0x05L1D_TLB_REFILL

L1 Data TLB refill:

1

This event is implemented.

[4]0x04L1D_CACHE

L1 Data cache access:

1

This event is implemented.

[3]0x03L1D_CACHE_REFILL

L1 Data cache refill:

1

This event is implemented.

[2]0x02L1I_TLB_REFILL

L1 Instruction TLB refill:

1

This event is implemented.

[1]0x01L1I_CACHE_REFILL

L1 Instruction cache refill:

1

This event is implemented.

[0]0x00SW_INCR

Instruction architecturally executed, condition check pass - software increment:

1

This event is implemented.


To access the PMCEID0_EL0 in AArch64 Execution state, read or write the register with:

MRS <Xt>, PMCEID0_EL0; Read Performance Monitor Common Event Identification Register 0

To access the PMCEID0 in AArch32 Execution state, read or write the CP15 register with:

MRC p15, 0, <Rt>, c9, c12, 6; Read Performance Monitor Common Event Identification Register 0

The PMCEID0_EL0 can be accessed through the external debug interface, offset 0xE20.

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