You copied the Doc URL to your clipboard.

12.3. AArch64 PMU register summary

The PMU counters and their associated control registers are accessible in the AArch64 Execution state with MRS and MSR instructions.

Table 12.3 gives a summary of the Cortex-A53 PMU registers in the AArch64 Execution state. For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table 12.3. PMU register summary in the AArch64 Execution state
NameTypeWidthDescription
PMCR_EL0RW32Performance Monitors Control Register
PMCNTENSET_EL0RW32

Performance Monitors Count Enable Set Register

PMCNTENCLR_EL0RW32

Performance Monitors Count Enable Clear Register

PMOVSCLR_EL0RW32

Performance Monitors Overflow Flag Status Register

PMSWINC_EL0WO32

Performance Monitors Software Increment Register

PMSELR_EL0RW32

Performance Monitors Event Counter Selection Register

PMCEID0_EL0RO32Performance Monitors Common Event Identification Register 0
PMCEID1_EL0RO32Performance Monitors Common Event Identification Register 1
PMCCNTR_EL0RW64

Performance Monitors Cycle Count Register

PMXEVTYPER_EL0RW32Performance Monitors Selected Event Type and Filter Register
PMCCFILTR_EL0RW32

Performance Monitors Cycle Count Filter Register

PMXEVCNTR0_EL0RW32Performance Monitors Selected Event Count Register
PMUSERENR_EL0RW32

Performance Monitors User Enable Register

PMINTENSET_EL1RW32

Performance Monitors Interrupt Enable Set Register

PMINTENCLR_EL1RW32

Performance Monitors Interrupt Enable Clear Register

PMOVSSET_EL0RW32Performance Monitors Overflow Flag Status Set Register
PMEVCNTR0_EL0RW32Performance Monitors Event Count Registers
PMEVCNTR1_EL0RW32
PMEVCNTR2_EL0RW32
PMEVCNTR3_EL0RW32
PMEVCNTR4_EL0RW32
PMEVCNTR5_EL0RW32
PMEVTYPER0_EL0RW32

Performance Monitors Event Type Registers

PMEVTYPER1_EL0RW32
PMEVTYPER2_EL0RW32
PMEVTYPER3_EL0RW32
PMEVTYPER4_EL0RW32
PMEVTYPER5_EL0RW32
PMCCFILTR_EL0RW32

Performance Monitors Cycle Count Filter Register


Was this page helpful? Yes No