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A.1. About the signal descriptions

The tables in this appendix list the Cortex-A53 processor signals, along with their direction, input or output, and a high-level description.

Some of the buses include a configurable width field, <Signal>[CN:0], where CN = 0, 1, 2, or 3, to encode up to four cores. For example:

  • nIRQ[0] represents a core 0 interrupt request.

  • nIRQ[2] represents a core 2 interrupt request.

Some signals are specified in the form <signal>x where x = 0, 1, 2 or 3 to reference core 0, core 1, core 2, core 3. If a core is not present, the corresponding pin is removed. For example:

  • PMUEVENT0[29:0] represents the core 0 PMU event bus.

  • PMUEVENT3[29:0] represents the core 3 PMU event bus.

The number of signals changes depending on the configuration. For example, the AMBA 5 CHI interface signals are not present when the processor is configured to have an AMBA 4 ACE interface.

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