Table A.28 shows the clock and configuration signals for the ACP interface.
|ACLKENS||Input||AXI slave bus clock enable.|
ACP master is inactive and is not participating in coherency. There must be no outstanding transactions when the master asserts this signal, and while it is asserted the master must not send any new transactions:
This signal must be asserted before the processor enters the low power L2 WFI state.