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A.13.1. APB interface signals

Table A.34 shows the APB interface signals.

Note

You must balance all APB interface signals with respect to CLKIN and time them relative to PCLKENDBG.

Table A.34. APB interface signals
SignalDirectionDescription
nPRESETDBGInput

APB reset, active-LOW:

0

Apply reset to APB interface.

1

Do not apply reset to APB interface.

PADDRDBG[21:2]InputAPB address bus.
PADDRDBG31Input

APB address bus bit[31]:

0

Not an external debugger access.

1

External debugger access.

PCLKENDBGInputAPB clock enable.
PENABLEDBGInput

Indicates the second and subsequent cycles of an APB transfer.

PRDATADBG[31:0]OutputAPB read data.
PREADYDBGOutput

APB slave ready.

An APB slave can deassert PREADYDBG to extend a transfer by inserting wait states.

PSELDBGInputDebug bus access.
PSLVERRDBGOutput

APB slave transfer error:

0

No transfer error.

1

Transfer error.

PWDATADBG[31:0]InputAPB write data.
PWRITEDBGInput

APB read or write signal:

0

Reads from APB.

1

Writes to APB.


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