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A.3. Reset signals

Table A.2 shows the reset and reset control signals.

Table A.2. Reset and reset control signals
SignalDirectionDescription
nCPUPORESET[CN:0]Input

Processor powerup reset:

0

Apply reset to all processor logic[a].

1

Do not apply reset to all processor logic[a].

nCORERESET[CN:0]Input

Individual core resets excluding Debug and ETM trace unit:

0

Apply reset to processor logic[b].

1

Do not apply reset to processor logic[b].

nL2RESETInput

L2 memory system reset:

0

Apply reset to shared L2 memory system controller.

1

Do not apply reset to shared L2 memory system controller.

L2RSTDISABLEInput

Disable automatic L2 cache invalidate at reset:

0

Hardware resets L2 cache.

1

Hardware does not reset L2 cache.

WARMRSTREQ[CN:0]Output

Processor warm reset request

0

Do not apply warm reset.

1

Apply warm reset.

[a] Processor logic includes Advanced SIMD and Floating-point, Debug, ETM trace unit, breakpoint and watchpoint logic.

[b] Processor logic includes Advanced SIMD and Floating-point, but excludes Debug, ETM trace unit, breakpoint and watchpoint logic.


Note

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