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4.4.16. c14 registers

Table 4.144 shows the CP15 system registers when the processor is in AArch32 state and the value of CRn is c14. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

Table 4.144. c14 register summary
Op1CRmOp2NameResetDescription
0c00CNTFRQUNK

Timer Counter Frequency Register

 c10CNTKCTL-[a]

Timer Control Register

 c20CNTP_TVALUNK

Physical Timer TimerValue Register

  1CNTP_CTL

-[b]

Physical Timer Control Register

 c30CNTV_TVALUNK

Virtual Timer TimerValue Register

  1CNTV_CTL-[b]

Counter-timer Virtual Timer Control Register

 c80PMEVCNTR0UNKPerformance Monitor Event Count Registers
  1PMEVCNTR1UNK
  2PMEVCNTR2UNK
  3PMEVCNTR3UNK
  4PMEVCNTR4UNK
  5PMEVCNTR5UNK
 c120PMEVTYPER0UNK

Performance Monitor Event Type Registers

  1PMEVTYPER1UNK
  2PMEVTYPER2UNK
  3PMEVTYPER3UNK
  4PMEVTYPER4UNK
  5PMEVTYPER5UNK
 c157PMCCFILTR0x00000000Performance Monitor Cycle Count Filter Register.
4c10CNTHCTL

-[c]

Timer Control Register (EL2)
 c20CNTHP_TVALUNKPhysical Timer TimerValue (EL2)
  1CNTHP_CTL-[b]Physical Timer Control Register (EL2)

[a] The reset value for bits[9:8, 2:0] is 0b00000.

[b] The reset value for bit[0] is 0.

[c] The reset value for bit[2] is 0 and for bits[1:0] is 0b11.


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