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Appendix D. Revisions

This appendix describes the technical changes between released issues of this book.

Table D.1. Issue A
ChangeLocationAffects

First release

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Table D.2. Difference between issue A and issue B
ChangeLocationAffects

Deleted NIC-301 inside MPCore clusters.

Figure 2.2All revisions

Changed description of Cortex-A15 L2 controller.

Cortex-A15 L2 cache controllerAll revisions

Added description of Cortex-A7 L2 controller.

Cortex-A7 L2 cache controllerAll revisions

Changed description of System Counter Control Registers.

Table 3.44All revisions

Table D.3. Differences between issue B and issue C
ChangeLocationAffects
Updated daughterboard memory map.Table 3.1All revisions

Table D.4. Differences between issue C and issue D
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Clarified that user can access NOR Flash 0 at two memory locations.

Overview of daughterboard memory map.

Table 3.1

All revisions
Corrected Cortex-A7 cluster version number.

Cortex-A15_A7 MPCore test chip

Cortex-A7 cluster

All revisions
Updated interrupt table.Table 2.11All revisions

Table D.5. Differences between issue D and issue E
ChangeLocationAffects
Corrected default value of register bit BROADCASTOUTER for MPCore A15 and MPCore A7.

Figure 3.20

Table 3.23

Figure 3.22

Table 3.25

All revisions
Corrected definition of CoreSight Debug enable register bitTable 3.12All revisions

Corrected default value of IMINLN bit in MPCore A15 configuration register 0.

Table 3.22

Figure 3.19

All revisions

Corrected test chip reset value of MPCore A15 configuration register 0.

Table 3.7

All revisions

Added default value of boot cluster bit in the system information register.

Table 3.29

All revisions

Added default value of boot core bits in the system information register.

Table 3.29

All revisions


Table D.6. Differences between issue E and issue F
ChangeLocationAffects
Added description of bits[15:11] of system information register.

Figure 3.26

Table 3.29

All revisions

Table D.7. Differences between issue F and issue G
ChangeLocationAffects
Corrected introductory text to register table.System timer register summaryAll revisions

Table D.8. Differences between issue G and issue H
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Corrected interrupt information.

Overview of interrupts

Figure 2.13

Table 2.11

All revisions

Table D.9. Difference between Issue H and Issue I
ChangeLocationAffects

Corrected memory test chip peripheral areas of memory maps.

Overview of daughterboard memory map.

Overview of the memory map for the on-chip peripherals.

All board versions.

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