The TBU and TCU are the major functional blocks of the MMU-500. The TBU caches frequently used address ranges and the TCU performs the page table walk.
Figure 2.1 shows the block diagram for MMU-500.
The MMU-500 applies the following logical processing steps to every transaction that flows in:
Determines the security state of the device that originates the transaction. The security attribute presented on AWPROT and ARPROT is different from the security state of the device. Identifying the security state of the device is called security state determination.
Maps an incoming transaction to one of the contexts using an incoming stream ID.
Caches frequently used address ranges using the TLB. The best-case hit latency of this caching is two clocks when the TBU address slave register slices are not specified. The best-case latency is three clocks when the TBU address slave register slices are specified.
Performs the main memory PTW automatically on an address miss.
Shares with the processor the page table formats as specified in the Large Physical Address Extension (LPAE) for maximum efficiency.
For more information on LPAE addresses, see the following documents:
ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.
ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.
Applies the required fault handling for every transaction.
Performs debug and performance monitoring through programmable performance counters, and reports statistics. For example, TLB refills or number of read or write accesses.