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2.2.3. Common interfaces

The MMU-500 supports the following interfaces that are common to TBUs and the TCU:

Low-power interface for clock gating and power control

The MMU-500 contains Low-power interfaces that enable:

  • Power gating of the TBU module.

  • Clock gating of the TBU module.

  • Clock gating of the TCU module.

You can control the power-control interfaces at the system level by a system power-control module. Alternatively, if there is no system control block, you must tie the qreqn_* inputs HIGH, and can leave the outputs, qacceptn_* and qactive_*, unconnected.

The MMU-500 never denies a powerdown request, and therefore you must tie LOW the qdeny_* input to the system power controller.

You must powerup the TCU module to powerup a TBU module.


The LPI signals are not synchronized. The system must provide the synchronous signals to the MMU-500.

The MMU-500 provides low-power interface and clock gating support in the following manner:

  • The TBU and TCU have dedicated Q-channel interfaces for clock gating:

    • qreqn_tbu_<tbuname>_cg, qacceptn_tbu_<tbuname>_cg, and qactive_tbu_<tbuname>_cg.

    • qreqn_tcu, qacceptn_tcu, and qactive_tcu.

  • The TBU and the clock or power bridge each have a dedicated Q-channel interface for entering the power-down state:

    • qreqn_tbu_<tbuname>_pd and qacceptn_tbu_<tbuname>_pd.

    • qreqn_pd_slv_br_<tbuname> and qacceptn_pd_slv_br_<tbuname>.

    • qreqn_pd_mst_br_<tbuname> and qacceptn_pd_mst_br_<tbuname>.


    If the TBU in separate clock and power domains option is disabled, you must tie the qreqn_tbu_<tbuname>_pd and qreqn_pd_br_<tbuname> signals HIGH.

  • The clock or power bridge contains the following qactive signals:

    • The qactive_br_tbu_<tbuname> signal for handling the cross-boundary clock wakeup to wakup the TBU clock.

    • The qactive_br_tcu_<tbuname> signal for handling the cross-boundary clock wakeup to wakeup the TCU clock.

Figure 2.3 shows the possible clock and power domains of the MMU-500.

Figure 2.3. Clock and power domains of the MMU-500

Figure 2.3. Clock and power domains of the MMU-500

Figure 2.4 shows a scenario in which the TBU0 and the TCU share a common clock or power domain and a PTW read channel.

Figure 2.4. Sharing a common clock or power domain and PTW read channel

Figure 2.4. Sharing a common clock or power domain
and PTW read channel

See the following documents for more information about low-power interface:

  • ARM® Low Power Interface Specification.

  • ARM® CoreLink MMU-500 System Memory Management Unit Integration Manual.

Performance interface

This interface contains the input signal spniden, which indicates whether security events need to be considered in the performance counters.

The performance interface also contains an event output interface that provides updates from each TBU to the performance counters.See Performance event signals and Authentication interface signal for more information.

Tie-off signal interface

This interface provides configuration information about certain functionality. See Tie-off signals for more information.

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