The MMU-500 supports the following TCU interfaces:
The MMU-500 requires a programming interface to permit the software to configure the controller and to initialize the memory devices. See Modes of operation and execution for information about using the 64-bit AXI4 programming interface.
The MMU-500 provides 32-bit address buses, awaddr_prog[31:0] and araddr_prog[31:0], but it only uses bits[23:2]. The MMU-500 ignores:
Bits[31:24], but their presence facilitates the process of integrating the MMU-500 with adjacent RTL blocks, such as an interconnect.
Bits[1:0], because the MMU-500 only permits word accesses to its internal registers.
This interface operates at the same frequency as the TCU clock.
This interface provides global, per-context, and performance interrupts. See Interrupt signals for more information.