The MMU-500 routes each translation through the following logical processing steps:
Security state determination.
Page table walk, if the translation is not cached in the TLB.
Attribute generation or merging, depending on the programming.
You can configure the MMU-500 to bypass the transaction process for a transaction or to fault a transaction regardless of the translation state.
The primary function of the MMU-500 is to provide address translations from an input address to an output address, based on address mapping and memory attribute information stored in translation tables.
The MMU-500 uses the following steps to achieve this:
Receives an address transaction, along with security and stream information.
Uses the security information received along with a transaction to determine the further processing steps for the transaction. The received security information is the security state of the originator of a transaction. The MMU-500 uses a Secure or Non-secure set of registers, for additional processing of a transaction, depending on the security state of the originator is Secure or Non-secure, respectively. See Security determination for more information.
Uses the stream information received along with the transaction to determine the translation mechanism to apply to the transaction. The translation mechanism can be a bypass, a stage 1 translation, a stage 2 translation, or a stage 1 followed by stage 2 translation. See the ARM® System Memory Management Unit Architecture Specification for more information.
Adds the fault information to the Global Fault Status Register if a fault is identified in the translation process before a context is mapped. The MMU-500 adds the fault information to the Context Banks Fault Status Register if a fault is identified after the context mapping.
A fault results in an interrupt when interrupt reporting is enabled. You can clear interrupts by clearing the Fault Status Register.
See the ARM® System Memory Management Unit Architecture Specification for more information.
The MMU-500 supports both little and big endian translation tables. You can program endianness in the SMMU_CB
n_SCTLR register. See ARM® Architecture Reference Manual ARMv7-A and ARMv7-R editions for more information.
See the ARM® CoreLink™ MMU-500 System Memory Management Unit Technical Reference Manual Supplement for information about initialization and configuration.
This section describes how the ARM® CoreLink™ MMU-500 System Memory Management Unit operates, and contain the following subsections: