This section lists the operational features of the MMU-500 in the following sections:
Outstanding transactions are defined as transactions for which:
The physical address access is generated and accepted by the slave.
Write or read responses are stalled.
For every TBU, the MMU-500 supports 128 outstanding transactions each for write and read accesses.
The MMU-500 generates a PTW when accesses from the master result in a TLB miss. However, the MMU-500 supports only eight such parallel PTWs for a TBU. If eight PTWs are pending, a TLB miss on a channel indicates that the MMU-500 cannot accept additional transactions on the write or read channels.
The PTWs are initiated by multiple TBUs. Therefore, when there are multiple outstanding transactions in the PTW queue, priority is given to the TBU with the highest QoS. The MMU-500 also reuses the programmed QoS value for PTWs.The arqosarb signal, a sideband signal from the MMU-500 to the CCI, has the highest QoS value compared to other read transactions in the MMU-500, including the transaction present on the PTW bus.
You can leave the unused output ports unconnected.
For address translations, the MMU-500 uses the programmed QoS value.For individual prefetch accesses, the MMU-500 uses the QoS value of the hit transaction.For transactions within the same QoS, the MMU-500 uses a first-come, first-served model.
The incoming address width is fixed at 49-bits, where A specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48-bits and the width of the AC address bus is 48-bits.
The MMU-500 does not support peripherals whose address width is greater than 49 bits.
You can program the QoS value to be used for each TBU PTW in the TCU. See TBU QoS registers.