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1.5. Configurable options

Table 1.1 shows the options that the MMU-500 implementer can configure. The configurable options of the MMU-500 are classified as follows:

  • TBU options.

  • TCU options.

Table 1.1. Configurable options
ParameterRangeDescription
TCU options
Number of configurable TBUs1-16Use this to select the number of unique TBU configurations. Each TBU configuration can be instantiated multiple times, using the TBU mapping.
Number of TBUs 1-32Use this to select the total number of TBUs.
TBU mapping1-16Each TBU can be mapped to a TBU configuration, using the configuration number.

StreamID - width of the sideband signal

1-10

Use this to select the width of the stream ID sideband signal on each TBU.

The stream ID is specified on the sideband signals, and dedicated sideband signals are used for read and write accesses. See Stream ID.

AXI programming interface ID signal width

1-23

Use this to select the programming interface AXI ID width.

PTW has a dedicated AXI port

Enable or disable

Use this to select a dedicated AXI interface for PTWs. This ensures that the other TBU0 AXI interface is reserved for device transactions.

PTW AXI data bus width

64 or 128

Use this to set the width, in bits, of the TCU AXI data bus that is used for PTWs.

This option is applicable only when the TCU has a dedicated AXI port for PTWs.

Only stage 2 translations

Enable or disable

Use this to configure the TCU to support stage 2 only or stage 1 followed by stage 2 translation. You can set the value to one of the following:

Enable

Only the stage 2 translation is supported.

Disable

All translations are supported.

Number of contexts

1, 2, 4, 8, 16, 32, or 64

Use this to specify the number of contexts. Select the value as one, only when the device is configured for Only stage 2 translations.

Number of SMRs

2, 4, 8, 16, 24, 32, 40, 48, 56, 64, or 128

Use this to set the number of Stream Mapping Registers (SMR) groups.

PTW depth

4, 8, 16, 24, or 32

Use this to set the number of PTWs.

Macro-TLB depth

0, 8, 128, 256, 512, 1024, or 2048

Use this to set the macro-TLB depth.

PTW cache depth

4, 32, 64, or 128

Use this to set the depth of the PTW cache, the IPA to PA translation cache, and the prefetch buffer.

TBU options

Name

NA

Use this to set the name of the TBU.

AXI ID signal width

1-23 bits

Use this to select the incoming AXI ID width.

AXI data bus width

64 or 128 bits

Use this to set the width, in bits, of the AXI data bus.

Depth of write buffer

0, 4, 8, or 16

Use this to select the depth of the write buffer.

The write buffer can accommodate multiple bursts up to the depth of the buffer.

The MMU-500 does not stall the write data path for transactions that the write buffer can hold.

The MMU-500 stalls transactions that cannot fit in the write buffer.

TLB depth

2, 8, 16, 32, 40, 48, 56, 64, or 128

Use this to specify the TLB depth.

Implement the TLB using the memory

Enable or disable

When enabled, you can implement the TLB using RAM. Otherwise, the MMU-500 implements the TLB as flip-flops.

Implementing the TLB as RAM optimizes area, but the setup and clock-to-Q delay is higher compared to using flip-flops.

Width of the AXI slave interface AWUSER signals

2-128 bits

Use this to set the width of the AXI slave interface AWUSER signals.

Note

You must set the input user width to two bits more than the required data width. See the AWUSER signal in the Table A.3.

Width of the AXI slave interface WUSER signals

1-128 bits

Use this to set the width of the AXI slave interface WUSER signals.

Width of the AXI slave interface BUSER signals

1-128 bits

Use this to set the width of the AXI slave interface BUSER signals.

Width of the AXI slave interface ARUSER signals

2-128 bits

Use this to set the width of the AXI slave interface ARUSER signals.

Note

You must set the input user width to two bits more than the required data width. See the ARUSER signal in the Table A.9.

Width of the AXI slave interface RUSER signals

1-128 bits

Use this to set the width of the AXI slave interface RUSER signals.

TBU in separate clock and power domains

Enable or disable

Enable this to configure a clock and power domain cross bridge between the TBU-TCU and TCU-TBU paths.

When disabled, the TBU and TCU are in the same clock and power domain.

Depth of the asynchronous first-in first-out buffer on the TCU to the TBU channel

0, 2, 4, or 10

Use this to configure a buffer in the clock and power domain cross bridge.

This option is applicable only when the TBU is in a separate clock and power domain.

TBU-TCU channel width

0, 1, or 2

Use this to configure the width of the data path between the TCU and the TBU, and the width of the serial data bus. You can set the width to one of the following:

0

Full width, 14 bytes. By selecting this option, you can send all TBU-TCU messages as one packet. The data width between TBU-TCU is HIGH, but the message delay can be LOW.

1

Half width, 7 bytes. By selecting this option, you can send all TBU-TCU messages as two packets. The data width is half of the full width option, and a trade-off between message delay and data width.

2

1 byte. By selecting this option, TBU-TCU messages can use maximum 14 clocks. The data width is only one byte, and used to connect lower priority TBUs.

Security options
SSD index signal width

0-10 bits

When you specify the SSD index signal width as 0, the Non-secure state is directly assigned to the incoming sideband signals along with the transaction.

Writes

Non-secure state = wsb_ns, where wsb_ns is the write sideband signal for security.

The Security State Determination (SSD) index is zero for a Secure access and it is one for a Non-secure master.

Reads

Non-secure state = rsb_ns, where rsb_ns is the read sideband signal for security.

The SSD index is zero for a Secure access and it is one for a Non-secure access.

The value driven on the sideband signal SSD index signal is used as a pointer into the SSD index table.You must configure at least one programmable or fixed Non-secure entry in the SSD index table.

Specify use of SSDIndex0-7

Specify SSDIndex0-7

Disable

Secure

Programmable-Secure

Programmable-Non-secure

Use this to specify Secure entries in the SSD index table. These options are applicable only when the width of the SSD index signal is greater than zero.

When the SSD index is determined, the SSD index table comprises bits from 0-2SSD index signal width-1. You must determine the status of all the bits as follows:

List of non-programmable indices:

  • For these indices, the security state of the master is defined and does not change.

  • You must specify the indices of the masters whose security states are always Secure.

List of programmable indices:

  • You can program the security state of these indices.

  • You must determine the default state of each master whose security state is programmable.

  • An SSD index is programmable or non-programmable, and is in the Secure or Non-secure state. By default, an SSD index is in the non-programmable Non-secure state.

For example, if the SSD index signal width is 6-bit, there are 64 indices in the range 0-63, whose security states must be determined.

TBU timing options

AWUSER slave interface registering options

Forward

Reverse

Full

Bypass

Each AXI channel has a configurable register slice in the MMU-500 slave interface.

An I/O delay of 70 percent of the clock is assumed for interfaces that are driven to, or driven by, a register.

An I/O delay of 40 percent of the clock is assumed for bypassed interfaces.

WUSER slave interface registering options

BUSER slave interface registering options

ARUSER slave interface registering options

RUSER slave interface registering options

TBU-TCU channel prebridge register slice 1 options

Forward

Reverse

Full

Bypass

Each TBU-TCU channel has 0-4 configurable register slices:

  • 0-2 register slices between the TBU and the clock and power domain cross bridge.

  • 0-2 register slices between the clock and power domain cross bridge and the TCU.

TBU-TCU channel prebridge register slice 2 options

TBU-TCU channel postbridge register slice 1 options

TBU-TCU channel postbridge register slice 2 options

TCU-TBU channel prebridge register slice 1 options

Forward

Reverse

Full

Bypass

Each TCU-TBU channel has 0-4 configurable register slices:

  • 0-2 register slices between the TCU and the clock and power domain cross bridge.

  • 0-2 register slices between the clock and power domain cross bridge and the TBU.

TCU-TBU channel prebridge register slice 2 options

TCU-TBU channel postbridge register slice 1 options

TCU-TBU channel postbridge register slice 2 options


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