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1.3. Features

The MMU-500 provides the following features:

  • Address virtualization to processors and other bus masters in the system.

  • Supports stage 1 translations, stage 2 translations, and stage 1 followed by stage 2 translations.

  • Programmable Quality of Service (QoS).

  • Distributed translation support for up to 32 TBUs.

  • Translation support for 32-bit to 49-bit virtual address ranges and 48-bit physical address ranges.

    See the following documents:

    • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

    • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R editions.

  • Multiple transaction contexts can apply to address translations for specific streams of transactions.

    • Supports up to 64 configurable contexts and programmable page size. The MMU-500 maps each context by using an input stream ID from the master device that requires address translation.

  • Translation support for the following:

    • Stage 1 ARMv7 VMSA.

    • ARMv8 AArch32.

    • AArch64 with 4KB and 64KB granules.

    • Stage 1 followed by stage 2 translations.

    See the following documents:

    • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

    • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R editions.

  • Supports 1-bit error detection in the TBU, and 1-bit error detection and correction in the TCU.

  • Supports 4KB, 64KB, 1MB, 2MB, 16MB, 512MB, and 1GB page sizes.

    See the following documents:

    • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

    • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R editions.

  • Arbitrates transactions from different TBUs by using the programmed QoS value.

  • Provides page table walk cache for storing intermediate page table walk data.

  • Caches page table entries in the TLB.

  • Supports TLB Hit-Under-Miss (HUM).

  • Provides configurable 4-32 PTW depth.

  • Provides TLB invalidation through the AMBA 4 DVM signalling or register programming.

    See the ARM® AMBA® AXI™ and ACE™ Protocol Specification AXI3™, AXI4™, and AXI4-Lite™ ACE™ and ACE-Lite™ for more information on the DVM.

  • Supports translation and protection checks including support for TrustZone® extensions.

  • Fault handling, logging, and signalling that includes demand paging and the support for the stall model.

  • Debug and performance-monitoring events.

  • One AMBA slave interface that supports ACE-Lite for connecting the bus master device that requires address translations.

    See the ARM® CoreLink™ MMU-500 System Memory Management Unit Implementation Guide for more information on connecting AXI3 or AXI4 devices.

  • One AMBA master interface for master device transactions or PTWs that support ACE-Lite and DVM.

    See the ARM® CoreLink™ MMU-500 System Memory Management Unit Implementation Guide for more information on connecting AXI3 or AXI4 devices.

  • An AXI4 interface for programming or configuration.

The MMU-500 is based on the ARM® System Memory Management Unit Architecture Specification.

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