The MMU-500 supports the AXI3 and AXI4 protocols when the sysbardisable_<tbuname> input signal is tied HIGH. In this mode, the following AXI3 features are not supported:
- Write data interleaving
Write data and write address ordering must be the same, otherwise data corruption can occur.
- Locked transfer
The input interface on a TBU contains only one bit of the AWLOCK and ARLOCK signals to ensure compliance with the AXI4 specification. Therefore, locked transfers are not supported even when the sysbardisable_<tbuname> signal is HIGH.
- The WID signal generation
The MMU-500 does not generate the WID signals for the TBU write data channels because these signals are not required for AXI4 and ACE-Lite modes. You must add logic to generate the WID signal based on the WID signal values that are used for the address channel transfer, and use the values for each write data channel transfer for a transaction.
The MMU-500 does not support write data interleaving. Therefore, the MMU-500 generates write data transfers in the sequence that the write addresses are issued, so you can generate the WID signals using the AWID signal values.
Example 2.2 shows a scenario in which a FIFO is used to generate the WID signal.
You can use a FIFO to generate the WID signal. The width of the FIFO is equal to the width of the AWID signal. You must set the depth to the outstanding write transaction depth supported by the system.
The MMU-500 supports an outstanding write transaction depth of 256. However, this depth can be limited by the outstanding write transaction depth of the master connected to the MMU-500.
You can generate the WID signal by using the following steps:
Write the AWID signal values to the FIFO when the AWVALID and AWREADY signals are HIGH.
Generate the WID signal by using the data from the FIFO that the data read pointer points to.
Increment the read pointer when the final write data transfer occurs for the specified address, that is when the WREADY, WVALID, and WLAST signals are HIGH at the same time.