The MMU-500 supports the following interfaces that are common to TBUs and the TCU:
The MMU-500 contains Q-channel low-power interfaces that enable:
Power gating of the TBU module.
Clock gating of the TBU module.
Clock gating of the TCU module.
You can control the power-control interfaces at the system level by a system power-control module. Alternatively, if there is no system control block, you must tie the qreqn_* inputs HIGH, and can leave the outputs, qacceptn_* and qactive_* unconnected.
The MMU-500 never denies a powerdown request on any Q-channel, and therefore you must tie LOW the qdeny_* input to the system power controller.
The TCU module must be powered up before, or at the same time as, any TBU module is powered up. The TCU module must remain powered up while any TBU module is powered up.
The low-power interface signals are not synchronized. The system must provide the synchronous signals to the MMU-500.
The MMU-500 provides a Q-channel low-power interface for clock gating support, which is used in the following manner:
The TBU and TCU have dedicated low-power Q-channel interfaces for clock gating:
qreqn_tbu_<tbuname>_cg, qacceptn_tbu_<tbuname>_cg, and qactive_tbu_<tbuname>_cg.
qreqn_tcu, qacceptn_tcu, and qactive_tcu.
The TBU and the clock or power bridge each have a dedicated Q-channel interface for entering the powerdown state:
qreqn_tbu_<tbuname>_pd and qacceptn_tbu_<tbuname>_pd.
qreqn_pd_slv_br_<tbuname> and qacceptn_pd_slv_br_<tbuname>.
qreqn_pd_mst_br_<tbuname> and qacceptn_pd_mst_br_<tbuname>.
TBU in separate clock and power domainsparameter is disabled, you must tie the following signals HIGH:
The clock or power bridge contains the following qactive signals:
The qactive_br_tbu_<tbuname> signal for handling the cross-boundary clock wakeup to wake up the TBU clock.
The qactive_br_tcu_<tbuname> signal for handling the cross-boundary clock wakeup to wake up the TCU clock.
Figure 2.3 shows the possible clock and power domains of the MMU-500.
Figure 2.4 shows a scenario in which the TBU0 and the TCU share a common clock or power domain and a PTW read channel.
The multiplexer shown in Figure 2.4, is present in the design only, when
you disable the
PTW has a separate AXI port configuration
parameter. You can use the multiplexer to share the ACE-Lite interface
of TBU0 with the PTW interface generated by the TCU. In this case,
you must ensure that the TBU0 data width is same as that of the
See the following documents for more information about Q-channel low-power interface:
Low Power Interface Specification, ARM® Q-Channel and P-Channel Interfaces .
ARM® CoreLink MMU-500 System Memory Management Unit Integration Manual.
This interface contains the input signal spniden that specifies whether security events must be considered in the performance counters, and contains an event output interface that provides updates from each TBU to the performance counters.
This interface provides configuration information about AXI or ACE-Lite interface operations and page table walk coherency. See Tie-off signals for more information.