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1.1. About the MMU-500

The MMU-500 is a system-level Memory Management Unit (MMU) that translates an input address to an output address, by performing one or more translation table walks.

It supports the translation table formats defined by the ARM architecture, ARMv7 and ARMv8, and can perform:

  • Stage 1 translations that translate an input Virtual Address (VA) to an output Physical Address (PA) or Intermediate Physical Address (IPA).

  • Stage 2 translations that translate an input IPA to an output PA.

  • Combined stage 1 and stage 2 translations that translate an input VA to an output IPA, and then translate that IPA to a PA. The MMU-500 performs a translation table walk for each stage of the translation.

Address translation can span over two stages, namely stage1 and stage2. Address translation at each stage often requires multiple translation table lookups that are called the levels of lookup. Each level of stage 1 translation might require additional stage 2 translation.

In addition to translating an input address to an output address, a stage of address translation also defines the memory attributes of the output address. With a two-stage translation, the stage 2 translation can modify the attributes defined by the stage 1 translation.

A stage of address translation can be disabled, or bypassed, and the MMU-500 can define memory attributes for a bypassed stage of translation.

The MMU-500 uses inputs from the requesting master to identify a context. This context tells the MMU-500 what resources to use for the translation including such things as which translation tables to use.

For the stage 1 translations that are typically associated with application and Operating System (OS) level operation, the VA range can be split into two subranges, translated by TTBR0 and TTBR1, each with associated translation tables and control registers.

These features mean the MMU-500 can perform address translations with the following page size limitations, for memory accesses from either AArch32 state or from AArch64 state:

ARMv7 architecture

No page size restrictions. All page sizes are supported.

ARMv8 architecture

Apart from the 16KB page granule, all page sizes are supported.

Stage 1 translations are supported for both Secure and Non-secure translation contexts. Usually, the appropriate OS:

  • Defines the translation tables, in memory, for the stage 1 translations for its security state.

  • Programs the MMU-500 to configure those stage 1 translations, and then enables the translations.

Stage 2 translations are supported only for Non-secure translation contexts. The typical usage model for two stages of address translation is as follows:

  • The Non-secure operating system defines the stage 1 address translations for application level and operating system level operation. It does this assuming it is mapping from the VAs used by the processors to PAs in the physical memory system. However, it actually maps from VAs to IPAs.

    Note

    This means that all the addresses the OS uses in the translation tables that it defines are in the IPA address space, and require a stage 2 translation to map them to the PA address space.

  • The hypervisor defines the stage 2 address translations that map the IPAs to PAs. It does this as part of its virtualization of one or more Non-secure guest operating systems.

The MMU-500 can cache the result of a translation table lookup in a Translation Lookaside Buffer (TLB) that means the MMU-500 also supports TLB maintenance operations.

For more information about:

  • The supported architectural features of the MMU-500, see the ARM® System Memory Management Architecture Specification.

  • Address translation, including the translation table formats and TLB maintenance operations, see:

    • The ARM® Architecture Reference Manual, ARMv7-A and ARMv-7 R edition.

    • The ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

The MMU-500 has the following key components:

Translation Buffer Unit (TBU)

The TBU contains a Translation Look-aside Buffer (TLB) that caches page tables. The MMU-500 implements a TBU for each connected master, and a TBU can be implemented so that it is local to the master rather than local to the TCU.

Translation Control Unit (TCU)

Controls and manages the address translations. The MMU-500 implements a single TCU.

Interconnect

Connects the multiple TBUs to the TCU.

Figure 1.1 shows the block diagram for the MMU-500.

Figure 1.1. MMU-500 block diagram

Figure 1.1. MMU-500 block diagram

See Chapter 2 Functional Description for more information about logical processing steps, interfaces, and operational features.

The following are example masters for the MMU-500:

  • Graphics Processor Unit (GPU).

  • Video engines.

  • Direct Memory Access (DMA) controllers.

  • Color LCD (CLCD) controllers.

  • Network controllers.

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