Following are the options that the MMU-500 implementer can configure:
TCU Options
Number of configurable TBUsNumber of TBUsStream ID - width of the sideband signalAXI ID signal width of the programming interfacePTW has a separate AXI portPTW AXI data bus widthOnly stage 2 translationsNumber of contextsNumber of SMR groupsWalk caches depthMacro TLB depthPTW depthTCU half clock
TBUn Mapping
Instance u_tbun
TBU CFGn Options
NameAXI ID signal widthAXI data bus widthDepth of the write bufferTLB depthTBU queue depthImplement the TLB using a memoryWidth of the AXI slave interface AWUSER signalsWidth of the AXI slave interface WUSER signalsWidth of the AXI slave interface BUSER signalsWidth of the AXI slave interface ARUSER signalsWidth of the AXI slave interface RUSER signalsTBU in a separate clock and power domainDepth of the asynchronous fifo buffer on the TCU to the TBU channelSerial data bus widthSSD index signal widthNumber of stages for synchronizationSpecify use of SSDIndex0-7Specify SSDIndex0-7
TBU CFGn Timing
AWUSER slave interface registering optionsWUSER slave interface registering optionsBUSER slave interface registering optionsARUSER slave interface registering optionsRUSER slave interface registering optionsTBU-TCU channel pre-bridge register slice 1 optionsTBU-TCU channel pre-bridge register slice 2 optionsTBU-TCU channel post-bridge register slice 1 optionsTBU-TCU channel post-bridge register slice 2 optionsTCU-TBU channel pre-bridge register slice 1 optionsTCU-TBU channel pre-bridge register slice 2 optionsTCU-TBU channel post-bridge register slice 1 optionsTCU-TBU channel post-bridge register slice 2 options
For more information about the values and descriptions of the configurable parameters, see the ARM® CoreLink™ MMU-500 System Memory Management Unit Supplement to AMBA® Designer (ADR-400) User Guide.