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1.3. Features

The MMU-500 provides the following features:

  • Address virtualization to other masters in an ARM processor based system and other bus masters in the system.

  • Support for the following translations:

    • Stage 1.

    • Stage 2.

    • Stage 1 followed by stage 2.

  • Programmable Quality of Service (QoS).

  • Distributed translation support for up to 32 TBUs.

  • Translation support for 32-bit to 49-bit virtual address ranges and 48-bit physical address ranges.

  • Multiple transaction contexts to apply to address translations for specific streams of transactions.

    • Supports up to 128 configurable contexts and programmable page size. The MMU-500 maps each context by using an input stream ID from the master device that requires address translation.

  • Translation support for the following:

    • Stage 1 ARMv7 VMSA.

    • Stage 1 and Stage 2 ARMv8 AArch32.

    • Stage 1 and Stage 2 ARMv8 AArch64 with 4KB and 64KB granules.

    • Stage 1 followed by stage 2 translations.

  • No page size restrictions. All page sizes are supported apart from the 16KB page granule defined by ARMv8 architecture.

  • Arbitration of transactions from different TBUs by using the programmed QoS value.

  • Page table walk cache for storing intermediate page table walk data.

  • Page table entry cache in the TLB.

  • Support of TLB Hit-Under-Miss (HUM).

  • Configurable PTW depth using parallel PTWs.

  • TLB invalidation through the AMBA 4 DVM signalling or register programming.

  • Translation and protection check support including TrustZone® extension support.

  • Fault handling, logging, and signalling that includes demand paging and support for the stall model.

  • One AMBA slave interface that supports ACE-Lite per TBU for connecting the bus master device that requires address translations. See AXI3 and AXI4 support.

  • One AMBA master interface for master device transactions or PTWs that support ACE-Lite and DVM. See AXI3 and AXI4 support.

  • An AXI4 interface for programming or configuration.

  • The TBU micro TLB, the TCU macro TLB, and the walk cache RAMs support single bit error detection and invalidation on error detection. The TCU Multi FIFO (MFIFO) RAM supports single bit error detection and correction.

  • Debug and performance-monitoring events.

  • The TCU core can run at half the clock speed of the TCU external interfaces.

  • Page table entry cache in the TLB at two levels, namely macro TLB and micro TLB.

  • A prefetch buffer to prefetch the next 4K or 64K leaf page entry to reduce latency.

  • A IPA2PA cache to speed up stage 1 followed by stage 2 translations.

For more information, see the following documents:

  • ARM® CoreLink™ MMU-500 System Memory Management Unit Implementation Guide

  • ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite

  • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

  • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

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