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A.2. ACE-Lite signals

The ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite describes the AMBA ACE-Lite signals. The following sections describe the ACE-Lite signals:

For more information about the output ID width, see Output ID width.

The awuser_<tbuname>_s and aruser_<tbuname>_s input user signals consist of the following:

  • Input user-defined bits that are passed as is. This information is stored at bits[(INPUT_AUSER_WIDTH-3):0].

  • Input Transient attribute for outer and inner cacheable domains. This information is stored at bits[(INPUT_AUSER_WIDTH-1):(INPUT_AUSER_WIDTH-2)].

    Note

    If the system does not generate this information, you must tie-off bits[(INPUT_AUSER_WIDTH-1):(INPUT_AUSER_WIDTH-2)] to zero.

There is a 4-bit signal addition to the awuser_<tbuname>_m and aruser_<tbuname>_m input user signals to form the output user signal. Therefore, the output user signals consist of the following parts:

  • Output user-defined bits that are the same as the input user-defined bits. This information is stored at bits[(INPUT_AUSER_WIDTH-3):0].Output Transient attribute for outer and inner cacheable domains. This information is stored at bits[(INPUT_AUSER_WIDTH-1):(INPUT_AUSER_WIDTH-2)]. These bits are not the same as the input Transient attribute, but are translated just like other attributes, based on register programming and page tables.

    Note

    If the system does not use the Transient attribute, you can ignore the corresponding output signal.

  • Output cache attributes form the inner cacheable domain. The MMU-500 outputs this information at bits[(INPUT_AUSER_WIDTH+3):(INPUT_AUSER_WIDTH)].

    • The page tables provide the cacheability attributes for the outer and inner cacheability domains.

    • The arcache and awcache signals contain the outer cacheability domain attributes.

    • The MMU-500 appends the inner cacheability domain attributes to the user signal.