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3.3.1. Reset values

MMU-500 Identification registers

Table 3.1 shows the register field reset values for the MMU-500 Identification registers.

Table 3.1. Reset values of SMMU_IDR registers, both Secure and Non-secure
Register fieldBits[a]Reset values
SMMU_IDR0
SMMU_IDR0.SES[31]0x1
SMMU_IDR0.S1TS[30]
0x0

Stage 1 translation is not supported.

0x1

Stage 1 translation is supported.

SMMU_IDR0.S2TS[29]0x1
SMMU_IDR0.NTS[28]
0x0

Stage 1 followed by stage 2 translation is not supported.

0x1

Stage 1 followed by stage 2 translation is supported.

SMMU_IDR0.SMS[27]0x1
SMMU_IDR0.ATOSNS[26]0x1
SMMU_IDR0.PTFS[25:24]
0x0

Stage 1 followed by stage 2 translation is supported.

0x1

V7L and V7S supported, and V7L format supported.

SMMU_IDR0.NUMIRPT[7:0][23:16]0x01
SMMU_IDR0.CTTW[14]0x0
SMMU_IDR0.BTM[13]0x1
SMMU_IDR0.NUMSIDB[3:0][12:9]0xF
SMMU_IDR0.NUMSMRG[7:0][7:0]SMR DEPTH
SMMU_IDR1
SMMU_IDR1.PAGESIZE[31]0x0
SMMU_IDR1.NUMPAGENDXB[30:28]

The reset values for the following contexts are:

1-8 contexts

0x2.

9-16 contexts

0x3.

17-32 contexts

0x4.

33-64 contexts

0x5.

64-128 contexts

0x6.

SMMU_IDR1.NUMS2CB[7:0][23:16]0x0
SMMU_IDR1.SMCD[15]0x0
SMMU_IDR1.SSDTP[12]

The possible reset values for SMMU_sIDR1.SSDTP (Secure) are:

0x0

Number of SSD entries is zero.

0x1

Number of SSD entries is not zero.

The reset value for SMMU_IDR1.SSDTP (Non-secure) is 0x0.

Note

This bit is configuration-dependent. This bit can have one of the following reset values:

0

When the SSD table is not configured.

1

When the SSD table is configured.

SMMU_IDR1.NUMSSDNDXB[3:0][11:8]
SMMU_sIDR1.NUMSSDNDBB[3:0] (Secure)

0xF

SMMU_IDR1.NUMSSDNDBB[3:0] (Non-secure)

0x0

SMMU_IDR1.NUMCB[7:0]Number of contexts.
SMMU_IDR2
Reserved[31:15]0x0
SMMU_IDR2.PTFSv8_64kB[14]0x1
SMMU_IDR2.PTFSv8_16kB[13]0x0
SMMU_IDR2.TFSv8_4kB[12]0x1
SMMU_IDR2.UBS[11:8]0x5
SMMU_IDR2.OAS[7:4]0x5
SMMU_IDR2.IAS[3:0]0x5
SMMU_IDR7
SMMU_IDR7.MAJOR[7:4]0x2
SMMU_IDR7.MINOR[3:0]0x0

[a] The reserved bits are not shown in Table 3.1. See the ARM® System Memory Management Unit Architecture Specification for more information.


MMU-500 Performance Monitor registers

The reset value of the Performance Monitor registers is 0x0, except for the registers that Table 3.2 shows. See the ARM® System Memory Management Unit Architecture Specification for more information.

Table 3.2. Reset values of Performance Monitor Extension registers
Register fieldBits[a]Reset values
SMMU_PMCGCR.CGNC[27:24]0x4
SMMU_PMCEID0.EVENT[18:16]0x1
[10:8]0x1
[1:0]0x1
SMMU_PMAUTHSTATUS.SNI[7]0x1
SMMU_PMDEVTYPE.T[7:4]0x5
SMMU_PMDEVTYPE.C[3:0]0x6
SMMU_PMCFGR.NCG[31:24]Number of TBU - 1
SMMU_PMCFGR.UEN[19]0x0
SMMU_PMCFGR.SIDG[18:17]0x0
SMMU_PMCFGR.EX[16]0x1
SMMU_PMCFGR.CCD[15]0x0
SMMU_PMCFGR.CC[14]0x0
SMMU_PMCFGR.SIZE[13:8]0x1F
SMMU_PMCFGR.N[7:0](Number of TBU * 4) - 1
SMMU_PMCNTENSETx[31:0]0x0
SMMU_PMCNTENCLRx[31:0]0x0
SMMU_PMOVSSETx[31:0]0x0
SMMU_PMOVSCLRx[31:0]0x0

[a] The reserved bits are not shown in Table 3.2. See the ARM® System Memory Management Unit Architecture Specification for more information.


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