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3.3. Memory model

The address map of the programming interface is consistent with the ARM® System Memory Management Unit Architecture Specification.

In addition to the registers specified in the ARM® System Memory Management Unit Architecture Specification, the MMU-500 implements the following configuration, identification, debug, context, integration, performance, and control registers:

  • Non-secure Auxiliary Configuration Register (SMMU_ACR).

  • Secure Auxiliary Configuration Register (SMMU_sACR).

  • TBU-TLB Debug Read Pointer register (SMMU_DBGRPTRTBU).TBU-TLB Debug Read Data register (SMMU_DBGRDATATBU).

  • TCU-TLB Debug Read Pointer register (SMMU_DBGRPTRTCU).

  • TCU-TLB Debug Read Data register (SMMU_DBGRDATATCU).

  • Auxiliary Control Register (SMMU_CBn_ACTLR).

  • Integration Mode Control register (SMMU_ITCTRL).

  • Integration Test Input register (SMMU_ITIP).

  • Integration Test Output Global register (SMMU_ITOP_GLBL).

  • TBU Performance Interrupt register (SMMU_ITOP_PERF_INDEX).

  • Integration Test Output Context Interrupt registers (SMMU_ITOP_CXTnTOm_RAMx):

    • Register for contexts 0-31 (SMMU_ITOP_CXT0TO31_RAM0).

    • Register for contexts 32-63 (SMMU_ITOP_CXT32TO63_RAM1).

    • Register for contexts 64-95 (SMMU_ITOP_CXT64TO95_RAM2).

    • Register for contexts 96-127 (SMMU_ITOP_CXT96TO127_RAM3).

  • TBU QoS registers (SMMU_TBUQOSx):

    • TBU QoS register 0 (SMMU_TBUQOS0).

    • TBU QoS register 1 (SMMU_TBUQOS1).

    • TBU QoS register 2 (SMMU_TBUQOS2).

    • TBU QoS register 3 (SMMU_TBUQOS3).

  • Parity Error Checker Register (SMMU_PER).

  • TBU Power Status Register (SMMU_TBU_PWR_STATUS).

  • Component Identification registers (SMMU_CIDRn):

    • Component Identification register 0 (SMMU_CIDR0).

    • Component Identification register 1 (SMMU_CIDR1).

    • Component Identification register 2 (SMMU_CIDR2).

    • Component Identification register 3 (SMMU_CIDR3).

  • Peripheral Identification registers (SMMU_PIDRn):

    • Peripheral Identification register 0 (SMMU_PIDR0).

    • Peripheral Identification register 1 (SMMU_PIDR1).

    • Peripheral Identification register 2 (SMMU_PIDR2).

    • Peripheral Identification register 3 (SMMU_PIDR3).

    • Peripheral Identification register 4 (SMMU_PIDR4).

    • Peripheral Identification registers 5-7 (SMMU_PIDR5-7).

The MMU-500 does not support the following Global Space Invalidation registers for stage 2 configurations:










The SMMU_SCR1.NSNUMCBO bit field is RO for Only stage 2 translations configurations.

The MMU-500 is configured through a memory-mapped register frame. The total size of the MMU-500 address range depends on the number of implemented translation contexts.

The MMU-500 address map consists of the following equally-sized regions:

The global address space

The global address space is located at the bottom of the MMU-500 address space, at SMMU_BASE. See Figure 3.1.

The translation context bank address space

The translation context bank address space is located above the top of the global address space, at SMMU_TOP. See Figure 3.1.

Figure 3.1. MMU-500 address map

Figure 3.1. MMU-500 address map

You can determine the MMU-500 address range by reading the value of the following register fields:



    The PAGESIZE refers to the size of the internal memory map, not the MMU-500 translation granule size.


See the ARM® System Memory Management Unit Architecture Specification for more information.

You can program the context page size as 4KB or 64KB using the SMMU_SACR.PAGESIZE bit. This bit can be programmed only when the MMU-500 is inactive.


The MMU-500 ignores non-word aligned write accesses to any of the registers.