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3.4.3. Integration registers summary

Table 3.5 shows the integration registers in base offset order.

Table 3.5. Integration registers summary
NameTypeS or NSOffsetDescription
SMMU_ITCTRLRWNS/S0x2000Integration Mode Control Register
SMMU_ITIPRONS/S0x2004Integration Test Input register
SMMU_ITOP_GLBLWONS/S0x2008Integration Test Output Global register
SMMU_ITOP_PERF_INDEXWONS/S0x200CTBU Performance Interrupt register

SMMU_ITOP_CXTnTOm_RAMx

  • SMMU_ITOP_CXT0TO31_RAM0

  • SMMU_ITOP_CXT32TO63_RAM1

  • SMMU_ITOP_CXT64TO95_RAM2

  • SMMU_ITOP_CXT96TO127_RAM3

WONS/S

0x2010

0x2014

0x2018

0x201C

Integration Test Output Context Interrupt registers

SMMU_TBUQOSx

  • SMMU_TBUQOS0

  • SMMU_TBUQOS1

  • SMMU_TBUQOS2

  • SMMU_TBUQOS3

RWNS/S

0x2100

0x2104

0x2108

0x210C

TBU QoS registers
SMMU_PERRWNS/S0x2200Parity Error Checker Register
SMMU_TBU_PWR_STATUSRWNS/S0x2204TBU Power Status register