This section describes the clock and reset signals of the MMU-500.
Table A.1 shows the clock and reset signals of the TCU.
|cclk||1||I||Clock for the TCU.|
|cresetn||1||I||Reset for the TCU.|
Table A.2 shows the clock and reset signals of the TBU.
If configured to have a separate PTW AXI port, the clock supplied to TBU0 also clocks the multiplexer between TBU0 and the TCU.
PTW has a separate AXI port is
set to zero, then these two clocks and resets must be the same.